Integrated circuit device with improved clock signal control

• US 5,783,960 A
• Filed: 07/15/1997
• Issued: 07/21/1998
• Est. Priority Date: 11/28/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lackey, David E.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/893,307
• Time in Patent Office: 371 Days
• Field of Search: 327/291, 327/293, 327/295, 327/296, 327/202, 327/211-213, 327/256-259, 326/16, 371/22.3, 371/22.5
• US Class Current: 327/295
• CPC Class Codes: G01R 31/318552 Clock circuits details

Abstract

A remote clock signal generation means is provided which allows a plurality of clock signals to be generated remotely at the "leaf" level thereby removing the need to have multiple clock signals at the system, or "tree" level. More particularly, this system is designed for use in an LBIST circuit featuring LSSD master-slave clock control. This disclosure teaches a clock control method and structure in which the master and slave clocks are generated directly from the system clock after the clock powering logic to thereby avoid intrusion or modification effects associated with logical manipulation of the clock signals.

Claims

1. A semiconductor integrated circuit comprising:

a) an enabling signal generator;

b) signal distribution means for remotely distributing a plurality of enabling signals generated by said enabling signal generator and for remotely distributing a single externally applied oscillator clock signal; and

c) a plurality of remote pulse signal generators, wherein each said remote pulse signal generator includes means for receiving said plurality of enabling signals and said single externally applied oscillator clock signal from said signal distribution means and selectively outputting either a first pulse signal substantially identical in time and duration to a high level of said externally applied oscillator clock signal over a first output line, or a second pulse signal substantially identical in time and duration to a low level of said externally applied oscillator clock signal over a second output line, or both said first and second pulse signals.

2. The semiconductor integrated circuit of claim 1 wherein each said remote pulse signal generator further includes means for generating said first and second pulse signals within a single clock cycle of said single externally applied oscillator clock signal.

3. The semiconductor integrated circuit of claim 1 wherein each said remote pulse signal generator further includes means for generating said first pulse when a first enabling signal of said plurality of enabling signals is enabled and means for generating said second pulse signal when a second enabling signal of said plurality of enabling signal is enabled.

4. The semiconductor integrated circuit of claim 2 further comprising at least one scan chain comprised of a master latch and a slave latch wherein said first pulse signal controls said master latch and said second pulse signal controls said slave latch.

5. The semiconductor integrated circuit of claim 1 further comprising a plurality of master-slave latches receiving said first and second pulse signals and a combinational logic operatively connected to said plurality of master-slave latches.

6. The semiconductor integrated circuit of claim 5 wherein said second pulse signal causes data to be launched from a first master-slave latch into said combinational logic and said first pulse signal causes data to be captured from said combinational logic into a second master-slave latch.

7. A system for implementing built-in self test clock control comprising:

a) a clock control logic unit with input lines for receiving an externally generated oscillator clock signal and a testing input, and output lines for outputting a plurality of control signals;

b) a signal distribution tree with input lines for receiving said plurality of control signals and said externally generated oscillator clock signal and output lines for outputting said plurality of control signals and said externally generated oscillator clock signal to a plurality of remote locations; and

c) a plurality of clock splitting devices located at said plurality of remote locations, each of said clock splitting devices comprising input lines for receiving said plurality of control signals and said externally generated oscillator clock signal, and a first output line for selectively outputting a first pulse signal substantially identical in time and duration to a low level of a clock cycle of said externally generated oscillator clock signal and a second output line for selectively outputting a second pulse signal substantially identical in time and duration to a high level of said clock cycle of said externally generated oscillator clock signal.

8. The system of claim 7 wherein each of said clock splitting devices further comprises a third output line for selectively outputting a third pulse signal substantially identical in time and frequency of said externally generated clock signal said second and third output lines providing signals for performing at-speed scan operation.

9. The system of claim 7 wherein said plurality of control signals comprises a scan gate signal.

10. The system of claim 8 wherein said first, second and third pulse signals comprise a master clock signal, a slave clock signal and a scan clock signal, respectively.

11. The system of claim 7 wherein said first and second pulse signals are inputted into a scan chain having a master latch and a slave latch.

12. The system of claim 11 wherein a high level of said oscillator clock signal will cause data to be transferred from said slave latch into a combinational logic circuit and a low level of said oscillator clock signal will cause data to be transferred from said combinational logic circuit into said master latch.

13. A method for implementing remote clock control comprising the steps of:

generating an oscillator clock signal, said oscillator clock signal having a plurality of clock cycles wherein each clock cycle includes a first and second level;

generating a plurality of enabling signals;

remotely distributing said plurality of enabling signals and said oscillator clock signal to a plurality of remote locations;

at each of said plurality of remote locations, inputting said plurality of remotely distributed enabling signals and said remotely distributed oscillator clock signal into a remote clock splitting device;

selectively outputting from each said remote clock splitting device a first pulse signal over a first output line that is substantially identical in time and duration to the first level of a captured clock cycle of said oscillator clock signal; and

selectively outputting from each said remote clock splitting device a second pulse signal over a second output line substantially identical in time and duration to the second level of said captured clock cycle of said oscillator clock signal.

14. The method of claim 13 wherein said plurality of remotely distributed enabling signals includes LSSD test data.

15. The method of claim 13 further comprising the step of inputting said first and second pulse signals into a scan chain comprised of master-slave latches.

16. The method of claim 13 wherein said first pulse signal comprises an inverted oscillator clock signal.