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Method for estimating routability and congestion in a cell placement fo integrated circuit chip

  • US 5,784,289 A
  • Filed: 12/20/1996
  • Issued: 07/21/1998
  • Est. Priority Date: 09/07/1994
  • Status: Expired due to Term
First Claim
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1. A method for producing a cell placement for a microelectronic integrated circuit, said placement including a plurality of cells interconnected by nets of wiring, comprising estimating routing density in said placement by performing the steps of:

  • (a) superimposing a first set of spaced apart lines over said placement, wherein each of said lines is formed of a plurality of segments;

    (b) constructing bounding boxes around said nets;

    (c) calculating wiring densities required by each net for each segment respectively in accordance with a predetermined function; and

    (d) summing said wiring densities to produce total wiring densities required by all of said nets for each segment respectively.

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