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Two-device memory cell on SOI for merged logic and memory applications

  • US 5,784,311 A
  • Filed: 06/13/1997
  • Issued: 07/21/1998
  • Est. Priority Date: 06/13/1997
  • Status: Expired due to Fees
First Claim
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1. A memory cell comprising:

  • a first field-effect transistor having a source, a drain, a gate, and a body;

    a second field-effect transistor having a source connected to the body of the first field effect transistor, a gate for receiving an external write control signal, and a drain for receiving an external bit signal, for selectively charging the body of the first transistor between a depleted and non-depleted condition, in response to a voltage level of said external write control signal, based on said external bit signal.

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