Test converage of embedded memories on semiconductor substrates

• US 5,784,323 A
• Filed: 02/04/1997
• Issued: 07/21/1998
• Est. Priority Date: 05/25/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ternullo, Luigi Jr., Koch, Garrett Stephen, Connor, John, Adams, Robert Dean
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/795,367
• Time in Patent Office: 532 Days
• Field of Search: 365/189.04, 365/189.05, 365/189.07, 365/201, 365/238.5, 371/21.2, 371/21.5, 371/24, 371/25.5
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory'"'"'s DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory'"'"'s DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.

Claims

1. A device for testing memory having separate write cycles and read cycles at a given port, comprising:

first logic circuitry to generate and input first write data of a known value to memory during a write cycle,

second logic circuitry to generate and apply second write data to said memory during a read cycle which second write data is different from said first write data written to memory during said write cycle, and

third logic circuitry to read data from memory during said read cycle.

2. The device of claim 1 including circuitry to provide expect data that is the same as said first data written to said memory during said write cycle.

3. The device of claim 2 including logic circuitry to compare said expect data to the data read from said memory.

4. The device of claim 2 wherein said first write data and said expect data are both either logic "1" or logic "0" and said expect data is the inverse of the second write data.

5. The device of claim 4 wherein said circuitry to generate said second write data during said read cycle that is different from said expect data includes an XOR gate.

6. The device of claim 5 wherein said XOR gate is connected to provide said second write data generated during the read cycle as the inverse of the expect data.

7. The device of claim 2 including logic circuitry to generate said expect data on said read cycle that is the same as the first write data generated on said write cycle.

8. The device of claim 2 wherein said device has a plurality of different read cycles, and said circuitry to provide said expect data provides expect data that is different from said second write data on prescribed read cycles.

9. The device of claim 8 wherein said read cycles include ascending address read cycles and descending address read cycles, and said logic circuitry to generate said second write data different from said expect data includes logic circuitry to generate said second write data only on one of said ascending and descending address read cycles.

10. A method of testing a memory using successive write and read cycles at a given point comprising the steps of:

writing first write data of a known value to said memory for storage therein during a write cycle,

applying second write data to said memory during a subsequent read cycle which second write data is different from said first write data, and

reading data from said memory during said read cycle.

11. A method of claim 10 wherein expect data is provided during said read cycle that matches said first write data written to said memory during said write cycle.

12. A method of claim 11 wherein said expect data is compared with said data read from the memory during said read cycle.

13. The method of claim 10 wherein said first write data and said expect data are both binary "1" or binary "0", and wherein said second write data is the inverse of said expect data.

14. The method of claim 10, wherein said second write data is provided only during read cycles.

15. The method of claim 10 wherein said expect data generated on a write cycle has the same value as said first write data generated on said write cycle.

16. The method of claim 10 wherein said device has a plurality of different read cycles, and wherein said second write data and expect data have the same value on at least one of said different cycles.

17. The method of claim 16 wherein said different read cycles include ascending address cycles and descending address cycles, and wherein said second write data and said expect data are different on only one of said ascending or descending address cycles.