Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
First Claim
1. A memory circuit comprising:
- a memory array including a plurality of memory cells;
a refresh circuit coupled to said memory array and configured to refresh said plurality of memory cells;
a temperature sensor for generating a temperature signal indicative of a temperature; and
a control circuit coupled to said temperature sensor and to said refresh circuit, wherein said control circuit is configured to generate a refresh rate signal dependent upon said temperature signal generated by said temperature sensor;
wherein said refresh circuit is configured to vary a rate of said refresh of said of said plurality of memory cells depending upon said refresh rate signal;
a look-up table unit coupled to said control circuit, wherein said look-up table unit is configured to store a plurality of entries, wherein each of said plurality entries indicates a desired refresh rate for a particular corresponding temperature.
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Accused Products
Abstract
A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.
210 Citations
18 Claims
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1. A memory circuit comprising:
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a memory array including a plurality of memory cells; a refresh circuit coupled to said memory array and configured to refresh said plurality of memory cells; a temperature sensor for generating a temperature signal indicative of a temperature; and a control circuit coupled to said temperature sensor and to said refresh circuit, wherein said control circuit is configured to generate a refresh rate signal dependent upon said temperature signal generated by said temperature sensor; wherein said refresh circuit is configured to vary a rate of said refresh of said of said plurality of memory cells depending upon said refresh rate signal; a look-up table unit coupled to said control circuit, wherein said look-up table unit is configured to store a plurality of entries, wherein each of said plurality entries indicates a desired refresh rate for a particular corresponding temperature. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for refreshing memory cells in a memory circuit comprising:
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sensing a temperature; generating a signal indicative of said temperature; varying a refresh rate of said memory cells depending upon said signal indicative of said temperature, accessing a ROM look-up table to determine a desired refresh rate for said temperature. - View Dependent Claims (9, 10)
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11. A memory circuit comprising:
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a memory array including a plurality of memory cells, wherein each of said memory cells includes; a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when a read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when a write signal is asserted; an analog-to-digital converter coupled to detect a value indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values; a refresh circuit coupled to said memory array and configured to refresh said plurality of memory cells; a temperature sensor for generating a temperature signal indicative of a temperature; and a control circuit coupled to said temperature sensor and to said refresh circuit, wherein said control circuit is configured to generate a refresh rate signal dependent upon said temperature signal generated by said temperature sensor; wherein said refresh circuit is configured to vary a rate of said refresh of said plurality of memory cells depending upon said refresh rate signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification