Apparatus and method for accurate synchronization with inbound data packets at relatively low sampling rates

• US 5,784,422 A
• Filed: 08/05/1996
• Issued: 07/21/1998
• Est. Priority Date: 08/05/1996
• Status: Expired due to Term

• Current Assignee: Transcrypt International, Inc. (JVC Kenwood Corporation)
• Original Assignee: Transcrypt International, Inc. (JVC Kenwood Corporation)
• Inventors: Heermann, Douglas A.
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/692,539
• Time in Patent Office: 715 Days
• Field of Search: 375/219, 375/354, 375/355, 375/357, 375/362, 375/364, 375/365, 375/366, 375/367, 375/368, 375/371, 375/373, 375/376, 375/208, 370/503, 370/516, 370/518, 380/48, 348/512, 348/515, 348/536, 348/537
• US Class Current: 375/355
• CPC Class Codes: H03J 7/065 the counter or frequency divider being used in a phase locked loop
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

An apparatus and method for accurate synchronization with inbound audio data which packets at relatively low sampling rates. By using previously known information such as the time of arrival of the beginning of the data packet, a reference timer in a digital signal processor can be used to calculate a number of samples and/or portions thereof between a beginning reference time and the beginning of a data packet, and then calculate the timing error between the first sample point after the arrival of the data packet and the beginning of the data packet. Using this information, the actual arrival of the data packet can be derived and utilized to very accurately, within very small margins of error, synchronize the beginning of the data packet with the scrambling algorithm used in the receiver.

Claims

1. A method for accurate synchronization of an audio signal with periodic synchronization data bursts comprising data modulated into a carrier frequency, implemented in a receiver having a digital signal processor with a reference timer having a fixed rate, using a relatively low sampling rate and having prior knowledge of when a data burst will appear comprising:

beginning the reference timer at a time to which correlates t₀ with an occurrence of a sample point;

calculating the amount of time between t₀ and the previously known time a data burst will appear;

calculating number and/or fractions of number of sample points between t₀ and the previously known time a data burst will appear;

calculating a time Δ

t between the previously known time a data burst will appear and a next sample point;

converting Δ

t into a percentage of the time between sample points;

converting Δ

t to a corresponding phase accumulator value for the carrier frequency of the synchronization data so that a local oscillator of a phase locked loop starts at a correct phase and the receiver is accurately synchronized with the audio signal when transmitted.

2. An apparatus for accurate synchronization of an analog signal comprising an audio signal with periodic synchronization data bursts modulated into a carrier frequency, using relatively low sampling rates and having prior knowledge of when a data burst will appear comprising:

a transceiver including a receiving circuit for receiving the analog signal;

a digital signal processor in the receiving circuit;

a phase locked loop implemented in the digital signal processor to demodulate synchronization data in the data bursts in the analog signal;

a numerically controlled oscillator implemented in the digital signal processor and having a phase accumulator;

a fixed rate reference clock implemented in the digital signal processor;

the reference clock starting at a time to which is correlated to a sample point;

the digital signal processor sampling the analog signal at a relatively low sample rate related to the rate of the fixed rate clock;

the prior knowledge of when a data burst will appear being compared with t₀, and the comparison used to alter the phase accumulator to provide synchronization timing compensation for any difference found in the comparison.

3. A method of compensating for timing error to allow accurate synchronization of a receiver to a transmitted signal comprising scrambled audio with intermittent data bursts of synchronization data while sampling the transmitted signal at a relatively low sample rate compared to the frequency of data bursts comprising:

obtaining prior knowledge of a time t_d of a data burst relative to a reference time t₀ ;

coinciding t₀ with a sample point and sampling the transmitted signal at a fixed and known rate every t_s ;

dividing t_d by t_s to determine the number of samples taken over t_d ;

if the number of samples taken over t_d equals a whole number, setting a timing error Δ

t between a sample point and the beginning of synchronization to be zero;

if the number of samples taken over t_d does not equal a whole number, calculating Δ

t;

converting Δ

t to a percentage of a sample period t_s ; and

converting the percentage of a sample period into a value that can be used to compensate for the timing error to accurately synchronize the receiver to the transmitted signal.