Duplicate control and processing unit for telecommunications equipment
First Claim
1. In a duplicate control and processing unit for tele-communications equipment having peripheral devices controlled by the duplicate control and processing unit, wherein the duplicate control and processing unit consists essentially of two identical control units connected to the peripheral devices, wherein each control and processing unit includes a processing unit with a processing unit bus and the processing unit carries out processing necessary for operating and controlling the telecommunications equipment, and wherein a plurality of peripheral circuits are connected to the processing unit bus for assisting the processing unit in carrying out its control functions, the improvement which comprises:
- each processing unit including a configuration control circuit generating a respective copy selection signal directed to the peripheral circuits belonging to the control units assigned thereto, the copy selection signals having logical values selectively determining which of the processing units is an active processing unit taking control of the telecommunications equipment;
each processing unit further including a clock signal generator, two mutually microsynchronized microprocessors connected in parallel to a single bus including lines for parity control and a RAM containing control software, and the peripheral circuits comprising respective interface circuits towards said processing unit and other telecommunications equipment not belonging to the duplicate control uniteach peripheral circuit including a double gate access circuit having gates connected to said busses of said processing units, and said access circuit having a control input receiving the copy selection signal for electrically connecting the bus lines of the respectively active processing unit and electrically disconnecting the bus lines of the respective processing unit on standby;
the peripheral circuits being duplicated, and a duplicate RAM of the duplicated peripheral circuits being adapted to contain the data necessary at the active processing unit for operating the telecommunications equipment and the data processed during an operation thereof, and comprising a mass memory and circuits for interfacing with input/output terminals;
the respectively active processing unit accessing a copy of a duplicated peripheral circuit, independendly of whether it belongs to its own or to the duplicated control unit, sending to the respective peripheral which it intends to access a respective selection signal used by said access circuit for extending to the selected peripheral circuit the bus of the respectively active processing unit; and
the active processing unit performing synchronous write cycles in both copies of the peripheral data RAM, to allow fast recovery of an operating synchronism by said processing unit after being switched from standby to active.
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Accused Products
Abstract
A duplicate control and processing unit for telecommunications equipment consisting of two identical control units connected together is described. Each control unit (UC0, UC1) comprises a processing unit (UP0, UP1) which can be active or on standby, a peripheral data random access memory (RAM) for data processed during operation, and several peripheral circuits connected to the rest of the equipment. An EPROM (erasable programmable read-only memory) (CCL0, CCL1) in each processing unit contains the copy selection firmware. The data RAM and the peripheral circuits include a respective double gate access circuit (ACC0, ACC1) which allows selective access to the active processor only. The latter performs the writing cycles synchronously on both the duplicate data RAMs, allowing fast recovery of the operative synchronism by the standby processing unit, after switching due to failure of the active processing unit (FIG. 2).
56 Citations
6 Claims
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1. In a duplicate control and processing unit for tele-communications equipment having peripheral devices controlled by the duplicate control and processing unit, wherein the duplicate control and processing unit consists essentially of two identical control units connected to the peripheral devices, wherein each control and processing unit includes a processing unit with a processing unit bus and the processing unit carries out processing necessary for operating and controlling the telecommunications equipment, and wherein a plurality of peripheral circuits are connected to the processing unit bus for assisting the processing unit in carrying out its control functions, the improvement which comprises:
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each processing unit including a configuration control circuit generating a respective copy selection signal directed to the peripheral circuits belonging to the control units assigned thereto, the copy selection signals having logical values selectively determining which of the processing units is an active processing unit taking control of the telecommunications equipment; each processing unit further including a clock signal generator, two mutually microsynchronized microprocessors connected in parallel to a single bus including lines for parity control and a RAM containing control software, and the peripheral circuits comprising respective interface circuits towards said processing unit and other telecommunications equipment not belonging to the duplicate control unit each peripheral circuit including a double gate access circuit having gates connected to said busses of said processing units, and said access circuit having a control input receiving the copy selection signal for electrically connecting the bus lines of the respectively active processing unit and electrically disconnecting the bus lines of the respective processing unit on standby; the peripheral circuits being duplicated, and a duplicate RAM of the duplicated peripheral circuits being adapted to contain the data necessary at the active processing unit for operating the telecommunications equipment and the data processed during an operation thereof, and comprising a mass memory and circuits for interfacing with input/output terminals; the respectively active processing unit accessing a copy of a duplicated peripheral circuit, independendly of whether it belongs to its own or to the duplicated control unit, sending to the respective peripheral which it intends to access a respective selection signal used by said access circuit for extending to the selected peripheral circuit the bus of the respectively active processing unit; and the active processing unit performing synchronous write cycles in both copies of the peripheral data RAM, to allow fast recovery of an operating synchronism by said processing unit after being switched from standby to active. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification