Method for reducing the bandwidth requirement in a system including a video decoder and a video encoder

• US 5,784,571 A
• Filed: 12/14/1995
• Issued: 07/21/1998
• Est. Priority Date: 12/14/1995
• Status: Expired due to Fees

• Current Assignee: Minerya System Incorporated
• Original Assignee: Minerya System Incorporated
• Inventors: Quinard, Fabrice, Grundy, Kevin, Mantopoulos, Thierry
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): VO, HIEN XUAN
• Application Number:
  US08/572,432
• Time in Patent Office: 950 Days
• Field of Search: 395/473, 395/821, 395/828, 395/200.77, 348/584, 348/578, 348/479, 348/622, 348/384, 364/715.011, 364/715.02, 382/232, 345/202, 341/50, 358/426, 370/477
• US Class Current: 709/247
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

In a video system having an encoder and multiple decoders, a snooping circuit in each decoder compares an address on a common data bus to determine whether encoded video data is read or written by a host computer. When the address on the common data bus is detected to be an address within a predetermined range, the read or write data on the common data bus is latched into a first-in-first-out (FIFO) memory. A decoding circuit in each decoder decodes from the FIFO memory to provide a decoded video data output stream. In this manner, multiple decoders can be supported by the video system without additional bandwidth demand on the host computer.

Claims

1. A video system including one or more decoders for decoding encoded video data, each decoder comprising:

an interface to an external bus having an address portion and a data portion;

a memory unit coupled to said external bus for receiving said encoded video data on said data portion of said external bus, said memory unit receiving said encoded video data when an asserted enable signal is received;

a snooping circuit coupled to receive an address on said address portion of said external bus, said snooping circuit providing said asserted enable signal when said address is an address within a predetermined address range; and

a video data circuit for decoding said encoded video data received in said memory unit into a decoded video data stream.

2. A video system as in claim 1, further comprising:

a video data encoder, being assigned said address in said predetermined address range, for encoding a video data stream to provide said encoded video data; and

a host computer for controlling said video system, said host computer causing said encoded video data to be placed on said data portion of said external bus in a read operation of said external bus effectuated by placing said address on said address portion of said external bus.

3. A video system as in claim 1, wherein each decoder further comprising:

a mass storage system for storing said encoded video data; and

a host computer for controlling said video system, said host computer retrieving said encoded video data from said mass storage system and causing, in a write operation on said external bus, said encoded video data and said address to be placed on said data portion of said external bus and said address portion of said external bus, respectively.

4. A video system as in claim 1, wherein each decoder further comprises an analog video output circuit for providing an analog output signal from said decoded video data stream.

5. A video system as in claim 1, wherein said memory unit comprises a first-in-first-out (FIFO) memory.

6. A method for providing one or more decoders to decode video data, said method comprising, in each decoder, the steps of:

interfacing said decoder to an external bus, said external bus having an address portion and a data portion;

coupling a memory unit to receive from said external bus said encoded video data on said data portion of said external bus, said memory unit receiving said encoded video data when an asserted enable signal is received;

comparing an address on said address portion of said external bus with selected bits of a stored address within a predetermined address range, said snooping circuit comparison confirms that said address is within said predetermined address range; and

decoding said encoded video data received in said memory unit into a decoded video data stream.

7. A method as in claim 6, further comprising the steps of:

assigning a video encoder said address in said predetermined address range, said video encoder encoding a video data stream to provide said encoded video data; and

providing a host computer to control said video system, said host computer causing said encoded video data to be placed on said data portion of said external bus in a read operation of said external bus effectuated by placing said address on said address portion of said external bus.

8. A method as in claim 6, wherein each decoder further comprising:

storing said encoded video data in a mass storage system; and

providing a host computer to control said video system, said host computer retrieving said encoded video data from said mass storage system and causing, in a write operation on said external bus, said encoded video data and said address to be placed on said data portion of said external bus and said address portion of said external bus, respectively.

9. A method as in claim 6, further comprising the step of providing said decoded video data stream as an analog video output signal.

10. A method as in claim 6, wherein said memory unit comprises a first-in-first-out (FIFO) memory.