Method and apparatus for digital signal processing for integrated circuit architecture

• US 5,784,602 A
• Filed: 10/08/1996
• Issued: 07/21/1998
• Est. Priority Date: 10/08/1996
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Jaggar, David Vivian, Glass, Simon James
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/727,785
• Time in Patent Office: 651 Days
• Field of Search: 395/474, 395/483, 395/800, 395/750, 395/561, 395/570, 395/595, 395/553, 395/560
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A digital signal processing system is described in which a microprocessor unit 2 operating under control of microprocessor program instruction words controls data transfer to and from a data storage device 8 and the supply and fetching of data to and from a digital signal processing unit 4.

Claims

1. A method of performing digital signal processing, using a microprocessor unit and a digital signal processing unit, of signal data words stored in a data storage device to generate result data words, said method comprising the steps of:

(a) in said microprocessor unit;

(i) generating, under control of microprocessor unit program instruction words, address words for addressing storage locations storing said signal data words within said data storage device;

(ii) reading said signal data words from said addressed storage locations storing said signal data words within said data storage device;

(iii) supplying said signal data words to said digital signal processing unit; and

(iv) fetching, under control of microprocessor unit program instruction words, said result data words from said digital signal processing unit, and

(b) concurrent with the above steps performed by said microprocessor unit, said digital processing unit performing, under control of digital signal processing unit program instruction words, arithmetic logic operations including at least one of a convolution operation, a correlation operation and a transform operation upon said signal data words to generate result data words.

2. A method as claimed in claim 1, further comprising the step of said microprocessor unit supplying data words generated by said microprocessor unit to a digital signal processing unit.

3. A method as claimed in claim 1, further comprising the steps of said microprocessor unit:

generating address words for addressing storage locations for storing said result data words within said data storage device; and

writing said result data words to said addressed storage locations for storing said result data words within said data storage device.

4. A method as claimed in claim 1, wherein said signal data words represent at least one input analog signal.

5. A method as claimed in claim 4, wherein said at least one input analog signal is a continuously varying real time input signal.

6. A method as claimed in claim 1, wherein said result data words represent at least one output analog signal.

7. A method as claimed in claim 6, wherein said at least one output signal is a continuously varying real time output signal.

8. Apparatus for performing digital signal processing upon signal data words stored in a data storage device, said apparatus comprising:

(i) a microprocessor unit; and

(ii) a digital signal processing unit coupled to said microprocessor unit, wherein

said microprocessor unit is programmed to operate under control of microprocessor unit program instruction words, to generate address words for addressing storage locations within said data storage device and to control transfer of said signal data words between said digital signal processing unit and said data storage device; and

said digital signal processing unit is programmed to operate concurrently with operation of said microprocessor unit and under control of digital signal processing unit instruction words to perform arithmetic logic operations including at least one of a convolution operation, a correlation operation and a transform operation upon said signal data words fetched from said data storage device by said microprocessor unit to generate result data words.

9. Apparatus as claimed in claim 8, wherein said result data words are written to said data storage device by said microprocessor unit.

10. Apparatus as claimed in claim 8, wherein said signal data words represent at least one input analog signal.

11. Apparatus as claimed in claim 10, wherein said at least one input analog signal is a continuously varying real time input signal.

12. Apparatus as claimed in claim 8, wherein said result data words represent at least one output analog signal.

13. Apparatus as claimed in claim 12, wherein said at least one output signal is a continuously varying real time output signal.

14. Apparatus as claimed in claim 8, wherein said microprocessor unit is responsive to a multiple supply instruction word to supply a plurality of sequentially addressed signal data words to said digital signal processing unit.

15. Apparatus as claimed in claim 8, wherein said digital signal processing unit includes an multi-word input buffer.

16. Apparatus as claimed in claim 8, wherein said microprocessor unit is responsive to a multiple fetch instruction word to fetch a plurality of sequentially addressed result data words from said digital signal processing unit.

17. Apparatus as claimed in claim 8, wherein said digital signal processing unit includes an multi-word output buffer.

18. Apparatus as claimed in claim 8, wherein a multiplexer data/instruction bus links said data storage device and said digital signal processing apparatus for transferring said signal data words, said microprocessor unit program instruction words and said digital signal processing unit program instruction words to said digital signal processing apparatus.

19. Apparatus as claimed in claim 8, wherein said digital signal processing unit includes a bank of digital signal processing unit registers for holding data words upon which arithmetic logic operations are to be performed, said digital signal processing program instruction words including register specifying fields.

20. Apparatus as claimed in claim 19, wherein said digital signal processing unit includes an multi-word input buffer and said input buffer stores destination data identifying a destination digital signal processing unit register for each data word stored in said input buffer.

21. Apparatus as claimed in claim 20, wherein digital signal processing unit program instruction words that read a digital signal processing unit register include a flag indicating whether a data word stored in said digital signal processing unit register may be replaced with a data word stored in said input buffer having matching destination data.

22. Apparatus as claimed in claim 21, wherein if said input buffering contains a plurality of data words having matching destination data, then said digital signal processing unit register is refilled with that data word having matching destination data that was first to be stored in said input buffer.

23. Apparatus as claimed in claim 20, wherein said microprocessor unit is responsive to a multiple supply instruction word to supply a plurality of sequentially addressed signal data words to said digital signal processing unit and a multiple supply instruction word specifies a destination data for a first data word, said destination data being incremented for each subsequent data word stored in said input buffer as a result of said multiple supply instruction word.

24. Apparatus as claimed in claim 23, wherein said multiple supply instruction word also specifies a limit destination data value, said destination data being incremented for each subsequent data word until said limit destination value is reached, whereupon said destination data is reset to said destination data for said first data word before said destination data is further incremented.

25. Apparatus as claimed in claim 8, wherein if said digital signal processing unit is unable to receive a data word supplied from said microprocessor unit, then said microprocessor unit stalls.

26. Apparatus as claimed in claim 8, wherein if said digital signal processing unit is unable to supply a data word being fetched by said microprocessor unit, then said microprocessor unit stalls.

27. Apparatus as claimed in claim 15, wherein if said digital signal processing unit attempts to read a data word not present in said input buffer, then said digital signal processing unit stalls.

28. Apparatus as claimed in claim 17, wherein if said digital signal processing unit attempts to write a data word to said output buffer and said output buffer is full, then said digital signal processing unit stalls.

29. Apparatus as claimed in claim 27, wherein if said digital signal processing unit stalls, then said digital signal processing unit enters a power saving mode.

30. Apparatus as claimed in claim 8, comprising a digital signal processing unit cache memory for storing digital signal processing unit instruction words.

31. Apparatus as claimed in claim 30, wherein digital signal processing unit instructions may be prefetched to said digital signal processing unit cache memory in response to a prefetch instruction.

32. Apparatus as claimed in claim 20, wherein said digital signal processing unit is responsive to an instruction that performs at least one of:

(i) marks as empty a plurality of registers of said digital signal processing unit; and

(ii) outputs the contents of a plurality of registers of said digital signal processing unit.

33. Apparatus as claimed in claim 8, wherein said microprocessor unit and said digital signal processing unit are formed as a single integrated circuit.

34. Apparatus as claimed in claim 19, wherein said plurality of digital signal processing unit registers includes at least one X-bit data register and at least one Y-bit accumulate register, where Y is greater than X.