Multiple asynchronous event arbitrator

• US 5,784,624 A
• Filed: 01/31/1996
• Issued: 07/21/1998
• Est. Priority Date: 01/31/1996
• Status: Expired due to Fees

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Ledlow, Dallas L., Douglass, James M.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/594,959
• Time in Patent Office: 902 Days
• Field of Search: 395/293, 395/294, 395/296, 395/728, 395/729, 395/732
• US Class Current: 710/244
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

An arbitrator for selectively permitting access to a common resource by a priority device and two non-priority devices, includes a priority request reception device for receiving a priority request to access the resource by the priority device; two second request reception devices for receiving non-priority requests to access the resource by the two non-priority devices; a prioritizer coupled to receive indications of times when the priority request reception device receives the priority request and when the two non-priority request reception devices receive the non-priority requests, with the prioritizer permitting access to the resource by the priority device and non-priority device in a predetermined order.

Claims

1. A device for selectively permitting access to a common resource by a priority device and at least one non-priority device, said device comprising:

a. a priority request reception device for receiving a first request to access the common resource by the priority device;

b. at least one non-priority request reception device for receiving a second request to access the common resource by the at least one non-priority device;

c. a prioritizer coupled to receive indications of times when said priority request reception device receives said first request and to receive indications of times when said at least one non-priority request reception device receives said second request, said prioritizer prioritizing access to the common resource between the priority device and the at least one non-priority device; and

d. said prioritizer permitting access to the common resource by the priority device when said priority request reception device receives said first request, and further wherein said prioritizer permitting access to the resource by the at least one non-priority device when said at least one non-priority request reception device receives said second request and subsequent to completion of access to the common resource by the priority device if the priority device had access to the common resource upon reception of the second request.

2. A device as recited in claim 1, wherein:

a. said prioritizer includes a counter device for limiting the duration of said access to the common resource by the non-priority device.

3. A device as recited in claim 2, wherein:

a. said prioritizer includes a state machine controller responsive to said counter device for controlling said access to the common resource by the at least one non-priority device.

4. A device as recited in claim 1, wherein:

a. said priority request reception device is further operative to receive a reset request; and

b. said prioritizer includes delay circuitry for delaying access to the common resource by the at least one non-priority device until said priority request reception device receives said reset request.

5. A device as recited in claim 4, wherein:

a. said delay circuitry includes at least one latch.

6. A device as recited in claim 5, wherein:

a. said at least one latch includes flip-flop circuity.

7. A device as recited in claim 6, wherein:

a. said flip-flop circuitry is a CMOS flip-flop.

8. A device for selectively permitting access to a common resource by a priority device and at least one non-priority device, said device comprising:

a. a first reception means for receiving a first request to access the common resource by the priority device;

b. a second reception means for receiving a second request to access the common resource by the at least one non-priority device;

c. means for prioritizing access to the common resource between the priority device and the at least one non-priority device, said prioritizing means being coupled to said first reception means and said second reception means and being responsive to said first reception means receiving said first request and being responsive to said second reception means receiving said second request; and

d. said prioritizing means including circuitry to permit access to the common resource by the priority device when said first reception means receives said first request, and further to permit access to the resource by the at least one non-priority device when said second reception means receives said second request and subsequent to completion of access to the common resource by the priority device if the priority device had access to the common resource upon reception of the second request.

9. A device as recited in claim 8, wherein:

a. said prioritizing means includes a counter device for limiting the duration of said access to the common resource by the non-priority device.

10. A device as recited in claim 9, wherein:

a. said first reception means is further operative to receive a reset request; and

b. said prioritizing means includes delay circuitry for delaying access to the common resource by the at least one non-priority device until said first reception means receives said reset request.

11. A device as recited in claim 10, wherein:

a. said delay circuitry includes at least one latch.

12. A device as recited in claim 11, wherein:

a. said at least one latch includes flip-flop circuity.

13. A device as recited in claim 12, wherein:

a. said flip-flop circuitry is CMOS flip-flop circuitry.

14. A device as recited in claim 13, wherein:

a. said prioritizing means includes a state machine controller responsive to said counter device for controlling said access to the common resource by the at least one non-priority device.

15. A method for selectively permitting access to a common resource by a priority device and at least one non-priority device, comprising the steps of:

a. receiving a first request to access the resource by the priority device;

b. receiving a second request to access the resource by the at least one non-priority device;

c. prioritizing access to the common resource between the priority device and the at least one non-priority device responsive to the received first request and the received second request;

d. permitting access to the common resource by the priority device upon reception of the first request; and

e. permitting access to the common resource by the non-priority device upon reception of the second request and subsequent to completing access to the common resource by the priority device if the priority device had access to the common resource upon reception of the second request.

16. A method as recited in claim 15, further including the step of:

a. limiting the duration of the access to the common resource by the non-priority device to a predetermined period of time.

17. A method as recited in claim 16, further including the step of:

a. delaying access to the common resource by the at least one non-priority device until a reset request is received.