Method and structure for performing pipeline burst accesses in a semiconductor memory
First Claim
1. A memory system comprising:
- a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time; and
a pipeline-burst access circuit coupled to the memory array, wherein the pipeline-burst access circuit enables pipeline-burst read operations or pipeline-burst write operations to be performed with the same access latency across the entire address range of the memory array;
wherein the pipeline-burst access circuit comprises a read buffer to the memory array, wherein the read buffer stores a set of data values for an entire burst read sequence; and
wherein the read buffer comprises;
a first data storage circuit coupled to the memory array; and
a second data storage circuit coupled to the first data storage circuit,wherein the first and second data storage circuits are cascaded to form a double buffer circuit; and
wherein the pipeline-burst access circuit further comprises a read buffer control circuit coupled to the read buffer, the read buffer control circuit generating a first control signal which causes the set of data values to be stored in the first data storage circuit during a first clock cycle.
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Abstract
A method and structure for implementing pipeline burst read and write operations in a semiconductor memory having a memory cycle time substantially longer than its I/O data cycle-time. The memory system includes a read buffer which stores all data required for a read burst transaction. All read burst data is loaded from the memory to the read buffer at the beginning of each burst read access. The memory is then isolated from the read buffer and prepared to perform the next burst access. During this time, the read data values are provided to the I/O device from the read buffer. A double-buffering technique provides gap-less output data for consecutive pipeline-burst read transactions. The memory system uses a two-entry write buffer in a first in, first out manner for pipeline-burst write operations. Each write buffer entry stores data for an entire burst transaction and a corresponding address. The first entry stores the data and address for a current write transaction and the second entry stores the data and address for a previous write transaction. The first and second entries are isolated to allow the second entry to provide its data and address to the memory while the first entry stores its corresponding data and address. A high-bandwidth transfer rate between the second entry and the memory with time to prepare the memory for the next transaction.
132 Citations
28 Claims
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1. A memory system comprising:
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a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time; and a pipeline-burst access circuit coupled to the memory array, wherein the pipeline-burst access circuit enables pipeline-burst read operations or pipeline-burst write operations to be performed with the same access latency across the entire address range of the memory array; wherein the pipeline-burst access circuit comprises a read buffer to the memory array, wherein the read buffer stores a set of data values for an entire burst read sequence; and wherein the read buffer comprises; a first data storage circuit coupled to the memory array; and a second data storage circuit coupled to the first data storage circuit, wherein the first and second data storage circuits are cascaded to form a double buffer circuit; and wherein the pipeline-burst access circuit further comprises a read buffer control circuit coupled to the read buffer, the read buffer control circuit generating a first control signal which causes the set of data values to be stored in the first data storage circuit during a first clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory system comprises:
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a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time; and a pipeline-burst access circuit coupled to the memory array, wherein the pipeline-burst access circuit enables pipeline-burst read operations or pipeline-burst write operations to be performed with the same access latency across the entire address range of the memory array; wherein the pipeline-burst access circuit comprises a write buffer coupled to the memory array, wherein the write buffer stores a set of data values for an entire burst write sequence; wherein the write buffer is controlled to transfer a plurality of data values to the memory array simultaneously.
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19. A memory system comprising:
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a dynamic random access memory (DRAM); and a memory control sequencer for accessing the DRAM, wherein the memory control sequencer generates a row access signal and a column access signal for controlling the memory operations of the DRAM in response to a single external access signal and a clock signal; wherein the memory control sequencer comprises circuitry for detecting the reception of the external access signal during a first cycle of the clock signal, asserting the row access signal during the first cycle and a consecutive second cycle of the clock signal, asserting the column access signal during the second cycle of the clock signal, de-asserting the row and column access signals during a consecutive third cycle of the clock signal, and precharging the DRAM during the third cycle of the clock signal.
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20. A memory system comprises:
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a dynamic random access memory (DRAM); and a memory control sequencer for accessing the DRAM wherein, the memory control sequencer generates, a row access signal and a column access signal for controlling the memory operations of the DRAM in response to an external access signal and a clock signal; wherein the memory control sequencer comprises circuitry for blocking the external access signal for three clock cycles upon detecting the external access signal.
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21. A method of operating a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time, the method comprising the steps of:
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initiating a read access to the memory array during a first clock cycle; reading a first set of data values from the memory array during a second clock cycle; storing the first set of data values read from the memory array in a first data storage circuit during the second clock cycle; storing the first set of data values in a second data storage circuit during the second clock cycle, wherein the second data storage circuit is cascaded with the first data storage circuit; and
thenisolating the second data storage circuit from the first data storage circuit during a third clock cycle. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method of operating a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time, the method comprising the steps of:
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storing a first set of data values in a first data storage circuit during a first write transaction; storing a first address corresponding to the first set of data values in a first address storage circuit during the first write transaction; shifting the first set of data values from the first data storage circuit to a second data storage circuit during the first write transaction; shifting the first address from the first address storage circuit to a second address storage circuit during the first write transaction; providing the first set of data values and the first address to the memory array during a second write transaction, whereby the first set of data values are written to the memory array during a single clock cycle; storing a second set of data values in the first data storage circuit during the second write transaction; storing a second address corresponding to the second set of data values in the first address storage circuit during the second write transaction; shifting the second set of data values from the first data storage circuit to a second data storage circuit after the first set of data values has been provided to the memory array; and shifting the second address from the first address storage circuit to a second address storage circuit after the first address has been provided to the memory array. - View Dependent Claims (28)
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Specification