Advanced copper interconnect system that is compatible with existing IC wire bonding technology

• US 5,785,236 A
• Filed: 11/29/1995
• Issued: 07/28/1998
• Est. Priority Date: 11/29/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Ming-Ren, Cheung, Robin W.
• Primary Examiner(s): Heinrich, Samuel M.
• Application Number:
  US08/564,695
• Time in Patent Office: 972 Days
• Field of Search: 228/180.5, 228/208, 228/110.1, 228/111, 437/209, 29/874, 29/884, 29/885, 438/637, 438/688
• US Class Current: 228/180.5
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48747 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. A process is provided to modify the copper pads so that conventional wire bonding techniques can be employed. In the process of the present invention an aluminum pad is formed over the copper interconnects. The metal wire is then bonded to the aluminum pad using conventional wire bonding techniques. No new hardware and/or technology is required for the metal wire bonding. No new technology is required to integrate the process of the invention into existing IC fabrication processes.

Claims

1. A process for forming electrical connection between metal wires and metal interconnects which cannot otherwise be bonded to form electrical contact therebetween, said metal wires and said metal interconnects supported over an integrated circuit structure, said metal interconnects supported in an interlayer dielectric, said process comprising:

(a) forming at least one of said metal interconnects within said interlayer dielectric;

(b) depositing a layer of aluminum on said metal interconnects and said interlayer dielectric;

(c) patterning and etching said layer of aluminum to form an aluminum pad;

(d) depositing an insulating layer over said aluminum pad, said metal interconnects, and said interlayer dielectric;

(e) patterning and etching said insulating layer to form a bonding pad opening in said insulating layer above said aluminum pad; and

(f) bonding one of said metal wires to said aluminum pad.

2. The process of claim 1 wherein said metal interconnects comprise copper interconnects.

3. The process of claim 1 wherein said metal wires are selected from the group of wires consisting of gold wires and aluminum wires.

4. The process of claim 1 wherein said metal interconnects are supported in an interlayer dielectric.

5. The process of claim 4 wherein said interlayer dielectric comprise dielectrics selected from the group consisting of oxide, nitride, oxynitride, polymers, and spin-on glass.

6. The process of claim 5 wherein said interlayer dielectric comprise dielectrics selected from the group consisting of CVD oxide, silicon dioxide, fluorinated silicon dioxide, silicon nitride, silicon oxynitride, and benzocylobutene.

7. The process of claim 5 wherein said interlayer dielectric is deposited by chemical vapor deposition or spin-on techniques.

8. The process of claim 4 wherein said metal interconnects are formed in said interlayer dielectric by a process comprising:

(a) depositing said interlayer dielectric;

(b) patterning and etching said interlayer dielectric to form trenches therein;

(c) blanket depositing a layer of metal over said interlayer dielectric to fill said trenches; and

(d) polishing or etching said layer of metal at least down to said interlayer dielectric to remove said excess metal outside of said trenches.

9. The process of claim 1 wherein a second insulating layer is formed which surrounds said aluminum pad by a process comprising:

(a) depositing said second insulating layer over said aluminum pad and said first insulating layer; and

(b) patterning and etching said second insulating layer to form a bonding pad opening in said first insulating layer above said aluminum pad.

10. The process of claim 1 wherein said integrated circuit structure comprises said integrated circuit devices formed in a semiconductor substrate, said integrated circuit devices including doped regions in said semiconductor substrate separated by field oxide.

11. The process of claim 10 wherein said integrated circuit structure includes multilayer interconnects comprising multiple levels of metal interconnects, each level of said metal interconnects supported by a separate said interlayer dielectric.

12. A process for forming electrical connection between metal wires and metal interconnects which cannot otherwise be bonded to form electrical contact therebetween, said metal wires and said metal interconnects supported over an integrated circuit structure, said metal interconnects supported in an interlayer dielectric, said process comprising:

(a) forming at least one of said metal interconnects within said interlayer dielectric;

(b) depositing a first insulating layer on said metal interconnects and said interlayer dielectric;

(c) patterning and etching said first insulating layer to form openings is said first insulating layer;

(d) blanket depositing a layer of aluminum on said first insulating layer and said openings in said first insulating layer;

(e) patterning and etching said layer of aluminum to form an aluminum pad; and

(f) bonding one of said metal wires to said aluminum pad.

13. The process of claim 12 wherein a second insulating layer is formed which surrounds said aluminum pad by a process comprising:

(a) depositing said second insulating layer over said aluminum pad and said first insulating layer; and

(b) patterning and etching said second insulating layer to form a bonding pad opening in said first insulating layer above said aluminum pad.

14. The process of claim 12 wherein said metal interconnects comprise copper interconnects.

15. The process of claim 12 wherein said metal wires are selected from the group of wires consisting of gold wires and aluminum wires.

16. The process of claim 12 wherein said metal interconnects are supported in an interlayer dielectric.

17. The process of claim 16 wherein said interlayer dielectric comprise dielectrics selected from the group consisting of oxide, nitride, oxynitride, polymers, and spin-on glass.

18. The process of claim 17 wherein said interlayer dielectric comprise dielectrics selected from the group consisting of CVD oxide, silicon dioxide, fluorinated silicon dioxide, silicon nitride, silicon oxynitride, and benzocylobutene.

19. The process of claim 17 wherein said interlayer dielectric is deposited by chemical vapor deposition or spin-on techniques.

20. The process of claim 16 wherein said metal interconnects are formed in said interlayer dielectric by a process comprising:

(a) depositing said interlayer dielectric;

(b) patterning and etching said interlayer dielectric to form trenches therein;

(c) blanket depositing a layer of metal over said interlayer dielectric to fill said trenches; and

(d) polishing or etching said layer of metal at least down to said interlayer dielectric to remove said excess metal outside of said trenches.

21. The process of claim 12 wherein said integrated circuit structure comprises said integrated circuit devices formed in a semiconductor substrate, said integrated circuit devices including doped regions in said semiconductor substrate separated by field oxide.

22. The process of claim 21 wherein said integrated circuit structure includes multilayer interconnects comprising multiple levels of metal interconnects, each level of said metal interconnects supported by a separate said interlayer dielectric.