Laminated multilayer substrates

• US 5,786,238 A
• Filed: 02/13/1997
• Issued: 07/28/1998
• Est. Priority Date: 02/13/1997
• Status: Expired due to Term

• Current Assignee: General Dynamics Information Systems, Inc. (General Dynamics Corporation)
• Original Assignee: Generyal Dynamics Information Systems Incorporated
• Inventors: Pai, Deepak K., Denny, Ronald R., Webster, Clark F., Lufkin, Robert M., Krinke, Terrance A., Chevalier, Jeanne M., Schwartz, George F. III
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/799,128
• Time in Patent Office: 530 Days
• Field of Search: 438/118, 438/119, 438/108, 438/128, 438/612, 438/613, 438/614, 438/615, 438/616
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/063 of preperforated insulating layer
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4647 by applying an insulating layer around previously made via studs

Abstract

A process of laminating a large-layer-count (LLC) substrates includes formation of first and second vias through respective substrates. A conductive path is formed through each of the respective vias, and posts are formed on the respective vias, electrically connected to the respective conductive path. A non-flowable adhesive layer having an aperture is provided between the LLC substrates so that the posts confront each other through the aperture. The LLC substrates are pressed together through the non-flowable adhesive layer to mechanically bond them together, and so that the posts abut each other. Simultaneously, the posts are electrically bonded to each other in the aperture.

Claims

1. A process of interconnecting large-layer-count (LLC) substrates, comprising:

providing first and second LLC substrates, each having a top surface and a bottom surface;

forming a first via in the first LLC substrate and a second via in the second LLC substrate, the first and second vias extending through the respective first and second LLC substrates between the respective top and bottom surfaces;

forming a conductive path through each of the first and second vias between the respective top and bottom surfaces;

forming a first post on the top surface of the first LLC substrate over the first via and electrically connected to the conductive path formed through the first via, and a second post on the top surface of the second LLC substrate over the second via and electrically connected to the conductive path formed through the second via;

providing a non-flowable adhesive layer having an aperture;

positioning the non-flowable adhesive layer between the first and second LLC substrates so that the first and second posts confront each other through the aperture in the non-flowable film adhesive layer; and

simultaneously;

pressing the first and second LLC substrates together through the non-flowable adhesive layer so that the non-flowable film adhesive layer is adhesively bonded to the first and second LLC substrates and the first and second posts abut each other; and

bonding the posts to each other electrically.

2. The process of claim 1, wherein the non-flowable adhesive layer comprises B-stage material.

3. The process of claim 2, wherein the aperture in the non-flowable adhesive layer is laser drilled to cure the B-stage material along a perimeter of the aperture.

4. The process of claim 1, wherein the first and second posts each include a layer of solder.

5. The process of claim 4, wherein bonding the posts to each other electrically comprises heating the posts to reflow the layers of solder.

6. The process of claim 1, wherein the first and second posts each include a layer of a metal alloy.

7. The process of claim 6, wherein the step of bonding the posts to each other electrically comprises diffusing the layers of metal alloy.

8. The process of claim 1, including plating the top surface of the substrates with a layer of copper.

9. The process of claim 8, wherein the step of providing a conductive path through each of the first and second vias comprises plating side walls of the vias with copper to contact the copper layer plated on the top surface of the substrates.

10. The process of claim 9, further comprising filling the first and second vias with an epoxy material after plating the side walls of the vias.