Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package

• US 5,786,271 A
• Filed: 07/03/1996
• Issued: 07/28/1998
• Est. Priority Date: 07/05/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohida, Mitsuru, Aoki, Hideo, Iwasaki, Hiroshi
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Turner, Kevin F.
• Application Number:
  US08/675,213
• Time in Patent Office: 755 Days
• Field of Search: 437/183, 437/211, 437/212, 257/737, 257/738, 257/778, 438/613, 438/615, 438/108
• US Class Current: 438/615
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A semiconductor package has a wiring circuit containing a conductive terminal formed on a first face of a substrate and a flat external connecting terminal electrically connected to the wiring circuit formed on a second face. An electrode pad is formed on a first face of a semiconductor chip. This semiconductor chip is mounted on the substrate with its first face down to oppose the first face of the substrate. A ball bump as a protruded electrode formed on the conductive terminal of the substrate and a ball bump as a protruded electrode formed on the electrode pad of the semiconductor chip are connected by solid phase diffusion. And, a sealing resin layer is formed in the space between the substrate and the semiconductor chip opposed to each other with a second face of the semiconductor chip exposed.

Claims

1. A method for producing a semiconductor package having a semiconductor chip, which has an electrode pad formed on its first surface and is mounted face down on a substrate which has formed on its first surface a wiring circuit containing a conductive terminal and on its second surface a flat external connecting terminal, which is electrically connected to said wiring circuit, the method comprising the steps of:

(a) forming a first protruded electrode, which is solid and has a top surface, on the conductive terminal of said substrate by wire bonding and forming a second protruded electrode on the electrode pad of said semiconductor chip by selective plating,

(b) flattening said first protruded electrode,

(c) providing said substrate and said semiconductor chip so as to oppose said first protruded electrode to said second protruded electrode,

(d) pressing said substrate and said semiconductor chip to make a solid phase diffusion bonding of said first protruded electrode and said second protruded electrode,

(e) charging a sealing resin into a space between said substrate and said semiconductor chip opposed to each other with a second surface of said semiconductor chip exposed, and

(f) curing said charged resin,

wherein said substrate and said semiconductor chip are pressed while being heated in step (d), and a temperature for heating said substrate and said semiconductor chip is in a range of about 200°

to 400°

C. and a press load is in a range of 100 to 300 gf per bump.

2. The method as set forth in claim 1,

wherein said first electrode is made flat by pressing the top surface of said first electrode from above by a bonding tool in the step (b), and

pressing said substrate and said semiconductor chip by said bonding tool in the step (d).

3. The method as set forth in claim 1,

wherein the step of forming said protruded electrode in the step (a) comprises the steps of:

forming a resist film on the first surface of said semiconductor chip,

removing the resist film from part of the electrode pad of said semiconductor chip by photolithography, and

forming said second protruded electrode by growing an Au layer by a selective plating method on the part of the electrode pad where said resist film has been removed.