Semiconductor device comprising trench EEPROM

• US 5,786,612 A
• Filed: 04/16/1996
• Issued: 07/28/1998
• Est. Priority Date: 10/25/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Otani, Naoko, Katayama, Toshiharu
• Primary Examiner(s): MONIN, DONALD L JR
• Application Number:
  US08/633,093
• Time in Patent Office: 833 Days
• Field of Search: 257/316, 257/317, 257/318, 257/322, 257/326, 257/331
• US Class Current: 257/316
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors. The device configuration as above achieves reduction in area of the gate electrode portions (23) and further reduction in each level difference between both regions having and not having the gate electrode portion (23). Thus, reduction in level difference of each memory cell is achieved while reduction in area of each memory cell is ensured.

Claims

1. A semiconductor memory device, comprising:

an underlying layer of a first conductivity type;

a trench formed in said underlying layer, extending inward from a main surface of said underlying layer to a prescribed depth, having a prescribed width in a first direction of said main surface and extending along a second direction perpendicular to said first direction;

a first impurity diffusion layer region of a second conductivity type formed at least under a bottom surface of said trench in said underlying layer;

a first gate insulating film formed at least on a side surface of said trench along said second direction and a part of said bottom surface of said trench in a portion inside said trench located in a region for a gate electrode portion to be formed;

a floating gate electrode formed so as to cover at least an upper surface of said first gate insulating film in said portion inside said trench located in said region for said gate electrode portion to be formed;

a second gate insulating film formed at least on one side surface of said floating gate electrode along said second direction, without coming into contact with said upper surface of said first gate insulating film, and formed on the other part of said bottom surface of said trench, the other side surface of said trench opposed to said one side surfaces, and on an upper surface of said floating gate electrode extending along the main surface which is opposed to said bottom surface of said trench in said portion inside said trench located in said region for said gate electrode portion to be formed;

a control gate electrode formed at least on an upper surface of part of said second gate insulating film covering at least said one side surface of said floating gate electrode, said other part of said bottom surface of said trench and said other side surface of said trench in said portion inside said trench located in said region for said gate electrode portion to be formed; and

a second impurity diffusion layer region of the second conductivity type formed in said underlying layer, extending inward from said main surface of said underlying layer, and being adjacent to said first gate insulating film.

2. The semiconductor memory device of claim 1, wherein

said upper surface of said floating gate electrode extends to said main surface of said underlying layer,

said control gate electrode is also formed on a portion of said upper surface of said second gate insulating film provided on said upper surface of said floating gate electrode, and

none of said first gate insulating film, said second gate insulating film and said control gate electrode is formed on said main surface of said underlying layer outside said trench.

3. The semiconductor memory device of claim 2, wherein

said first impurity diffusion layer region is formed immediately below said bottom surface of said trench and further formed in another portion of said underlying layer below said second impurity diffusion layer region.

4. The semiconductor memory device of claim 1, wherein

said upper surface of said floating gate electrode and an upper surface of said control gate electrode are formed to a higher level in height than said main surface of said underlying layer,

said upper surface of said control gate electrode and said upper surface of said second gate insulating film provided on said upper surface of said floating gate electrode are at the same level in height from said main surface of said underlying layer, and

said first gate insulating film, said second gate insulating film, said floating gate electrode and said control gate electrode extend from said trench over said main surface of said underlying layer outside said trench along said first direction.

5. A semiconductor memory device, comprising:

a trench formed in an underlying layer, extending inward from a main surface of said underlying layer;

a gate insulating film formed inside said trench so as to divide a space inside said trench in half; and

two gate electrodes formed inside said trench so as to be opposed to each other with said gate insulating film therebetween.

6. The semiconductor memory device of claim 5, wherein

one of said two gate electrodes is formed extending over said trench from the inside thereof so as to cover the other gate electrode.