Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging

• US 5,786,628 A
• Filed: 10/16/1997
• Issued: 07/28/1998
• Est. Priority Date: 09/28/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cronin, John Edward, Leas, James Marc, Bertin, Claude Louis, Howell, Wayne John, Beilstein, Kenneth Edward Jr., Perlman, David Jacob
• Primary Examiner(s): Ostrowski, David
• Application Number:
  US08/951,663
• Time in Patent Office: 285 Days
• Field of Search: 257/686, 257/698, 257/723, 257/724, 257/725, 257/684, 257/778, 257/783
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Claims

1. A temporary workpiece for attaching to a substantially planar surface of a semiconductor structure having a plurality of contacts, said temporary workpiece comprising:

a temporary support;

a temporary adhesive layer disposed on a surface of said temporary support; and

a thin-film layer coupled to said temporary support by said temporary adhesive layer, wherein said thin-film layer can be transferred to said substantially planar surface of the semiconductor structure to interconnect at least some of said plurality of contacts by bonding said thin-film layer to said substantially planar surface and decoupling said temporary support from said thin-film layer along said temporary adhesive layer.

2. The temporary workpiece of claim 1, wherein said thin-film layer comprises a metallization layer, and wherein said metallization layer is configured to electrically connect to said semiconductor structure to interconnect said at least some of said plurality of contacts when bonded to said substantially planar surface of said semiconductor structure.

3. The temporary workpiece of claim 1, further comprising a plurality of electrical contacts disposed on said thin-film layer for establishing electrical contact to said semiconductor structure when said thin-film layer is bonded to said semiconductor structure.

4. The temporary workpiece of claim 1, further comprising a substrate disposed between said thin-film layer and said temporary adhesive layer, said substrate providing mechanical support for said thin-film layer when said temporary support is decoupled along said temporary adhesive layer from said thin-film layer.

5. The temporary workpiece of claim 4, further comprising an active circuit layer disposed between said substrate and said temporary adhesive layer, said active circuit layer functioning in association with said semiconductor structure when said temporary workpiece is electrically and mechanically attached thereto.

6. The temporary workpiece of claim 5, wherein said substrate includes a plurality of electrically conductive vias extending between said thin-film layer and said active circuit layer, said plurality of electrically conductive vias providing electrical contact between said thin-film layer and said active circuit layer.

7. The temporary workpiece of claim 5, further comprising a plurality of electrical contacts disposed on said active circuit layer for facilitating electrical coupling thereof to a circuit external from said semiconductor structure.

8. The temporary workpiece of claim 1, further comprising a passive film disposed between said thin-film layer and said temporary adhesive layer, said passive film providing mechanical support for said thin-film layer after said temporary support is decoupled along said temporary adhesive layer from said thin-film layer.

9. The temporary workpiece of claim 8, further comprising a metallization layer disposed between said passive film and said temporary adhesive layer, said metallization layer electrically connecting to said semiconductor structure when said temporary workpiece is electrically and mechanically attached thereto.

10. The temporary workpiece of claim 9, wherein said passive film includes a plurality of electrically conductive vias extending between said thin-film layer and said metallization layer, said plurality of electrically conductive vias providing electrical contact between said thin-film layer and said metallization layer.

11. The temporary workpiece of claim 9, further comprising a plurality of electrical contacts disposed on said metallization layer for facilitating electrical coupling thereof to a circuit external from said semiconductor structure.