Simulation corrected sensitivity

• US 5,787,008 A
• Filed: 04/10/1996
• Issued: 07/28/1998
• Est. Priority Date: 04/10/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: O'Brien, Peter R., Blaauw, David T., Dharchoudhury, Abhijit, Pullela, Satyamurthy, Norton, Joseph W., Edwards, Tim J.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/629,488
• Time in Patent Office: 839 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578
• US Class Current: 703/19
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.

Claims

1. A method for correcting sensitivity characteristic values associated with circuit elements, said circuit elements and associated sensitivities comprising a file from which selected ones of said elements are designated to be included in a model circuit for use in specifying circuit elements and connections therebetween for a circuit being designed, said circuit elements defining a plurality of paths within the circuit being designed, said method comprising:

determining a voltage relationship at each node within the circuit, where at least two of said circuit elements are coupled together at each node;

calculating approximate sensitivities for each of said circuit elements based on the voltage relationship at each corresponding node;

determining corrected sensitivities by applying a calculated correction factor;

selecting a most sensitive element on a non-critical path of the plurality of paths having a highest corrected sensitivity;

calculating a predicted circuit delay change based upon using said model circuit including said most sensitive element;

increasing said most sensitive element size;

determining actual delay time of said model circuit;

determining whether said delay time of said model circuit meets a predetermined threshold; and

terminating said method if said delay time of said model circuit meets said predetermined threshold, said method being further operable otherwise for;

calculating a correction factor based upon said predicted delay change and said actual delay change, said calculated correction factor being available for determining corrected sensitivities for said circuit elements.

2. The method as set forth in claim 1 and further including a step of:

applying said correction factor to said step of determining corrected sensitivities of said circuit elements.

3. The method as set forth in claim 1 and further including:

applying a first circuit model to determine a circuit signal propagation delay;

periodically testing an accuracy characteristic of said circuit signal propagation delay; and

applying a more accurate second circuit model whenever said accuracy characteristic is determined to be outside of a predetermined threshold level.

4. A storage medium which is selectively coupled to a processing circuit, said processing circuit including a medium reading device selectively operable to read said storage medium and provide program signals representative of indicia present on said storage media to the processing circuit, said storage medium being selectively operable in combination with said processing circuit for providing a method for correcting sensitivity characteristic values associated with circuit elements, said circuit elements and associated sensitivities comprising a file from which selected ones of said elements are designated to be included in a model circuit for use in specifying circuit elements and connections therebetween for a circuit being designed, said method comprising:

calculating complemenetary effective capacitive relationships for said circuit elements;

performing timing analysis for each of said circuit elements using the complementary effective capacitive relationships;

calculating approximate sensitivities for said circuit elements based on the timing analysis;

determining corrected sensitivities by applying a calculated correction factor;

selecting a most sensitive element having a highest corrected sensitivity, wherein the most sensitive element is on a non-critical path in the circuit being designed;

calculating a predicted circuit delay change based upon using said model circuit including said most sensitive element;

increasing said most sensitive element size;

determining actual delay time of said model circuit;

determining whether said delay time of said model circuit meets a predetermined threshold; and

terminating said method if said delay time of said model circuit meets said predetermined threshold, said method being further operable otherwise for;

calculating a correction factor based upon said predicted delay change and said actual delay change, said calculated correction factor being available for determining corrected sensitivities for said circuit elements.

5. The storage medium as set forth in claim 4 wherein said method further includes a step of:

applying said correction factor to said step of determining corrected sensitivities of said circuit elements.

6. A method for optimizing characteristics of a circuit being designed, said method comprising the steps of:

determining a required time at which a propagated input signal must arrive at predetermined nodes of a plurality of elements within the circuit, in order to enable the circuit to provide an output signal at a specified output time, said required time being measured from a predetermined input start time;

determining corresponding arrival times measured from said predetermined input start time, said corresponding arrival times being representative of times which said propagated input signal actually arrives at said predetermined nodes;

calculating a slack time at each of said predetermined nodes, said slack time being representative of a time difference between the arrival time and the required time;

selecting an element in accordance with a predetermined weighting function with regard to said slack times, wherein the element is on a non-critical path in the circuit; and

changing a characteristic of said selected element;

wherein said step of determining corresponding arrival times further includes;

calculating approximate sensitivities for said circuit elements;

determining corrected sensitivities by applying a calculated correction factor;

selecting a most sensitive element having a highest corrected sensitivity;

calculating a predicted circuit delay change based upon using said model circuit including said most sensitive element;

increasing said most sensitive element size;

determining actual delay time of said model circuit;

determining whether said delay time of said model circuit meets a predetermined threshold; and

terminating said method if said delay time of said model circuit meets said predetermined threshold, said method being further operable otherwise for;

calculating a correction factor based upon said predicted delay change and said actual delay change, said calculated correction factor being available for determining corrected sensitivities for said circuit elements.

7. The storage medium as set forth in claim 6 wherein said method further includes a step of:

applying said correction factor to said step of determining corrected sensitivities of said circuit elements.

8. A storage medium which is selectively coupled to a processing circuit, said processing circuit including a medium reading device selectively operable to read said storage medium and provide program signals representative of indicia present on said storage media to the processing circuit, said storage medium being selectively operable in combination with said processing circuit for optimizing characteristics of a circuit being designed, by accomplishing the steps of:

determining a required time at which a propagated input signal must arrive at predetermined nodes of a plurality of elements within the circuit being designed, in order to enable the circuit being designed to provide an output signal at a specified output time, said required time being measured from a predetermined input start time;

determining corresponding arrival times measured from said predetermined input start time, said corresponding arrival times being representative of times which said propagated input signal actually arrives at said predetermined nodes;

calculating a slack time at each of said predetermined nodes, said slack time being representative of a time difference between the arrival time and the required time;

selecting an element on a non-critical path of the circuit in accordance with a predetermined weighting function with regard to said slack times; and

changing a size characteristic said selected element;

wherein said step of determining corresponding arrival times further includes;

calculating approximate sensitivities for said circuit elements;

determining corrected sensitivities by applying a calculated correction factor;

selecting a most sensitive element having a highest corrected sensitivity;

calculating a predicted circuit delay change based upon using said model circuit including said most sensitive element;

increasing said most sensitive element size;

determining actual delay time of said model circuit;

determining whether said delay time of said model circuit meets a predetermined threshold; and

terminating said method if said delay time of said model circuit meets said predetermined threshold, said method being further operable otherwise for;

calculating a correction factor based upon said predicted delay change and said actual delay change, said calculated correction factor being available for determining corrected sensitivities for said circuit elements.

9. The storage medium as set forth in claim 8 wherein said method further includes a step of:

applying said correction factor to said step of determining corrected sensitivities of said circuit elements.