Ultra low power multiplier

• US 5,787,029 A
• Filed: 01/10/1997
• Issued: 07/28/1998
• Est. Priority Date: 12/19/1994
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Inventors: de Angel, Edwin
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/782,527
• Time in Patent Office: 564 Days
• Field of Search: 364/760, 364/759, 364/758, 364/757, 364/754, 364/707, 364/760.01, 364/760.02, 364/760.04
• US Class Current: 708/628
• CPC Class Codes: G06F 7/5338 each bitgroup having two new bits, e.g. 2nd order MBA

Abstract

A multiplier using a modified Booth algorithm dissipates power proportional to the magnitude of one of the operands, and logic races are eliminated using iterative networks.

Claims

1. A digital multiplier having an array of computational units arranged in rows and columns characterized in that the multiplication operation involves calculations which progresses in a first direction across a plurality of said rows, and wherein, depending on input data to said digital multiplier, some row calculations are suppressed in that the calculations in said suppressed row are not made, and output data from a row previous to said suppressed row are used in calculations of a row after said suppressed row.

2. The digital multiplier set forth in claim 1 wherein if two of said suppressed rows occur in a sequence in said first direction, the data from a row which is not suppressed which is a first such row immediately prior to said two suppressed rows is used in a calculation of a row which is not suppressed and which is immediately subsequent to said two suppressed rows.

3. The digital multiplier set forth in claim 1 wherein said computational units operate in an iterative manner such that each of said computational units provides a data valid signal to another of said computational units to enable a sequential operation of said computational units.

4. The digital multiplier set forth in claim 1 wherein each of said computational units receives a true and bitwise complement of a portion of multiplier data, and where in said digital multiplier further includes a carry propagate adder circuit coupled between outputs of said array of computational units, said multiplier data, and output terminals of said digital multiplier.

17. Apparatus set forth in claims 1, 2, 3, 4, 8, 9, 10, 11, 12, 13, 14, 15, or 16 wherein said multiplier is a parallel multiplier.

18. Apparatus set forth in claims 1, 2, 3, 4, 8, 9, 10, 11, 12, 13, 14, 15, or 16 wherein said multiplier is an array multiplier.

5. A method for digitally multiplying a multiplicand by a multiplier in an array of computational units arranged in rows and columns to produce a product comprising the steps of:

a) proceeding with calculations which progress in a first direction across a plurality of said rows; and

depending on multiplicand data

i) suppressing some row calculations such that calculations in said suppressed row are not made, and

ii) using data from a row previous to said suppressed row in a calculation of a row after said suppressed row.

6. The method set forth in claim 5 wherein if two of said suppressed rows occur in sequence, data from a first row previous to said suppressed rows which is not suppressed is used in a calculation of a first row subsequent to said suppressed row which is not suppressed.

7. The method set forth in claim 5 wherein in each of said rows which have not been suppressed, proceeding from a first side in said each of said rows to an opposite side in said each of said rows in an iterative manner such that each of said computational units provides a data valid signal to enable a next sequential computational unit.

19. The method set forth in claims 5, 6, or 7 wherein said multiplier is a parallel multiplier.

20. The method set forth in claims 5, 6, or 7 wherein said multiplier is an array multiplier.

8. In a digital multiplier having sequential row operation from a first row to a last row of a series of rows, the improvement comprising a plurality of multiplexers between two adjacent rows of said series of rows, each of said multiplexers having a first set of inputs coupled to an output of a row immediately previous to said multiplexer and a second set of inputs coupled to an output of a second previous row to said multiplexer, and an output coupled to an input in the next immediately successive row, and additional circuitry responsive to the multiplicand input data to said digital multiplier which has an output to said multiplexers which selects one of said first set of inputs and said second set of inputs.

9. In a digital multiplier having a series of rows, each of said rows having a plurality of computational circuitry,

each of said plurality of computational circuitry being in a preset state before a multiplication operation begins

the improvement comprising circitry coupled between a multiplicand and said plurality of computational circuitry in a particular row such that during a multiplication operation, each of said plurality of computational circuitry in a particular row either is held in said preset state by said circuitry or is allowed to become active to process data depending on said multiplicand.

10. The digital multiplier set forth in claim 9 wherein the power dissipated in each one of said computational circuitry is less when said one of said computational circuitry is held in a preset condition compared to the power dissipated in said one of said computational circuitry when said one of said computational circuitry is allowed to become active.

11. The digital multiplier set forth in claim 9 wherein

the power dissipated in each one of said computational circuitry during a first multiplication operation of said digital multiplier when said one of said computational circuitry is held in a preset state during said first multiplication operation is less

when the multiplication operation immediately previous to said first multiplication operation results in said one of said computational circuitry being held in a preset state

compared to the power dissipated in said one of said computational circuitry during a second multiplication operation

when the multiplication operation immediately previous to said second multiplication operation allows said one of said computational circuitry to become active.

12. A digital multiplier which receives input data of a multiplier and a multiplicand comprising:

a) a plurality of data cells in rows wherein a top row receives a portion of said input data of said multiplier and data derived from said input data of said multiplicand and provides output data to a next row; and

,

b) wherein each or said remaining rows receive portions of data input to, and portions of data output from, a row immediately previous to said each of said remaining rows, a portion of said input data of said multiplier, and input data derived from said input data of said multiplicand for each of said remaining rows; and

,

c) wherein said data cells in each of said remaining rows

i) process said output data from said row immediately previous to each of said remaining rows, a portion of said input data of said multiplier, and said data derived from said input data of said multiplicand, and ignore said data input to said row immediately previous to each of said remaining rows when a predetermined portion of said input data of said multiplicand is one of plurality of bit sequences, and

ii) process said input data to said row immediately previous to each of said remaining rows, a portion of said input data of said multiplier, and said data derived from said input data of said multiplicand, and ignore said data output from said row immediately previous to each of said remaining rows when a predetermined portion of said input data of said multiplicand is other than said one of plurality of bit sequences.

13. A digital multiplier having an array of cells, each of which have enable/disable inputs such that said each of said cells is active or inactive in response to the state of said enable/disable input, and a least one cell control circuit which provides said enable/disable inputs to at least one of said each of said cells in response to input data to said multiplier, and which is able, depending on said input data, to hold said at least one of said each of said cells inactive during an entire multiplication operation, and the power dissipated by each of said cells is substantially influenced by the state of said enable/disable input of each cell.

14. In a digital multiplier having an array of computational circuitry arranged in rows and columns, the improvement comprising additional circuitry which has inputs coupled to a portion of the input data to said digital multiplier, and having at least one output signal which selectively suppresses a subset of said computational circuitry such that said subset of computational circuitry are not enabled during an entire multiplication operation.

15. A digital multiplier having a plurality of cells and a cell control circuit having an input coupled to inputs of said digital multiplier and having an output to said plurality of cells wherein, depending on the input data bits of said cell control circuit, one or more of said cells is held in a preset condition during an entire multiplication operation in which others of said plurality of cells become active.

16. The digital multiplier set forth in claim 15 wherein each of said plurality of cells consists of an adder.