Method and apparatus for reading out a programmable resistor memory
First Claim
1. Circuitry for reading out a data bit stored in a memory cell of a memory array, comprising:
- a readout circuit including at least one sense node coupled to receive a readout signal from the memory cell; and
a detector circuit coupled to the sense node and operating when the readout signal achieves a threshold level indicative of the data bit stored in the memory cell to condition the readout circuit such that the sense node is driven to a logic signal level that reliably indicates a binary value of the stored data bit.
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Accused Products
Abstract
To read out a data bit stored in a memory cell including a programmable resistor memory element, a first voltage is developed on a first sense node due to initiation of current flow through the memory element and a second voltage is developed on a second sense node due to current flow through a reference resistor. The first and second voltages are separately detected to generate a trip signal in response to a leading edge of either of the first and second voltages achieving a threshold level. A flip-flop circuit is conditioned by the trip signal to produce opposite logic signal voltages on the first and second sense nodes indicative of the binary value of the stored data bit.
60 Citations
20 Claims
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1. Circuitry for reading out a data bit stored in a memory cell of a memory array, comprising:
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a readout circuit including at least one sense node coupled to receive a readout signal from the memory cell; and a detector circuit coupled to the sense node and operating when the readout signal achieves a threshold level indicative of the data bit stored in the memory cell to condition the readout circuit such that the sense node is driven to a logic signal level that reliably indicates a binary value of the stored data bit. - View Dependent Claims (2, 3, 4)
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5. A circuit for reading out a data bit stored in a programmable resistor memory element of a memory array, comprising:
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a comparator including a first sense node coupled to receive a readout signal from the memory element and a second sense node coupled to receive a reference signal; and a detector circuit coupled to the first and second sense nodes and operating when a leading edge of one of the readout and reference signals first achieves a threshold level to generate a trip signal, the comparator, in response to the trip signal, operating to drive the first sense and second sense nodes to opposite logic signal levels depending on an amplitude relationship of the readout and reference signals at the time of trip signal generation, the sense node logic signal levels being indicative of a binary value of the stored data bit. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of reading out a data bit stored in a memory cell of a memory array, comprising:
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initiating a readout signal from the memory cell during a readout cycle; detecting a leading edge of the readout signal; generating a trigger signal when the leading edge of the readout signal achieves a threshold level; and conditioning a readout circuit, in response to the trigger signal, to produce a logic signal indicative of a binary value of the stored data bit.
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17. A method of reading out a data bit stored by a programmable resistor memory element, comprising:
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coupling a first sense node to receive a readout signal from the memory element during a readout cycle; coupling a second sense node to receive a reference signal; detecting the readout signal developing on the first sense node; detecting the reference signal developing on the second sense node; generating a trigger signal when one of the developing readout and reference signals achieves a threshold; and driving the first and second sense nodes, in response to the trigger signal, to opposite logic signal levels indicative of a binary value of the stored data bit. - View Dependent Claims (18, 19, 20)
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Specification