Loop-back test system and method

• US 5,787,114 A
• Filed: 01/17/1996
• Issued: 07/28/1998
• Est. Priority Date: 01/17/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Pan, Rong, Ducaroir, Francois, Ramamurthy, Krishnan
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/586,174
• Time in Patent Office: 923 Days
• Field of Search: 375/220, 375/221, 375/222, 375/224, 375/377, 370/249, 370/366, 370/506
• US Class Current: 375/221
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: H04L 1/241 using pseudo-errors
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back

Abstract

A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver'"'"'s input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver'"'"'s input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Claims

1. A loop back test system for detection of intra-domain errors of an integrated I/O interface core of an integrated circuit, comprising in operative combination:

a) an integrated transmitter, said transmitter comprising;

i) a transmitter input stage for receiving transmitter input data, said input date encoded with an alignment pattern and said input data having a first format, and

ii) a transmitter converter stage for converting said transmitter input data into transmitter output data, said output data having a second format;

b) an integrated receiver, said receiver comprising;

i) a receiver converter stage for buffered receiving said transmitter output data for conversion of said transmitter output data to said first format to provide received reconverted data,

ii) a receiver alignment stage for extracting said alignment pattern from said received reconverted data, and for aligning said received reconverted data to conform to timing of said transmitter input data;

c) a first switching circuit in electrical cooperation with said transmitter converter stage having a first open condition, and a second closed condition, said second closed condition for shunting transmitter output data to said receiver converter stage to provide loop back data to said receiver converter stage, said first switching circuit second closed condition being enabled upon assertion of a loop back signal to the I/O interface core;

d) a second switching circuit in electrical cooperation with said receiver converter stage having a first open position to permit receipt of externally transmitted data, and a second closed condition for receiving an input test data for reconversion, and alignment of the reconverted input test data to provide an output test data, and for halting receipt of the externally transmitted data upon assertion of the loop back signal to the I/O interface core; and

e) an error analysis circuit for comparing said output test data with said input test data.

2. A loop back test system as in claim 1 wherein said I/O interface core is a serializer/deserializer interface core for converting alignment coded parallel formatted data to serial formatted data for transmission, and for converting serial formatted data to parallel formatted data for reception.

3. A loop back test system as in claim 2 further comprising an in-core built-in self-test (BIST) circuit for providing pseudo-random, alignment of encoded said input test data to said transmitter input stage.

4. A loop back test system as in claim 1 wherein said first switching circuit includes semiconductor switching devices, said first switching circuit being designed to maintain the direct current balance of the I/O interface core.

5. A loop back test system as in claim 4 wherein said semiconductor switching devices are MOSFET transistors.

6. A loop back test system as in claim 1 wherein said second switching circuit includes semiconductor switching devices, said second switching circuit being designed to maintain the direct current balance of the I/O interface core.

7. A loop back test system as in claim 6 wherein said semiconductor switching devices are MOSFET transistors.

8. A loop back test system as in claim 1 wherein said error analysis circuit is disposed in an in-core built-in self-test (BIST) circuit and includes an error counter and error trace buffer for determining and reporting the bit-error rate of the output test data as compared to the input test data.

9. A loop back test system for detection of intra-domain errors of an integrated I/O interface circuit core of an integrated circuit, comprising in operative combination:

a) means for transmitting data, said transmitting means comprising;

i) a transmitter input means for receiving input data, said input data encoded with alignment pattern, and said input data having a first format, and

ii) a data conversion means for converting said input data from said first format into a second format;

b) means for receiving transmitted data, said receiving means comprising;

i) a receiver conversion means for buffered receiving transmitted output data having said second format, and converting said transmitted output data from said second format to said first format to provide received reconverted data, and,

ii) a receiver data alignment means for extracting said encoded alignment pattern from the reconverted data, and for aligning the reconverted data to conform to timing of said transmitter input data timing;

c) a first switching means in electrical cooperation with said data conversion means for switching converted input test data from said data conversion means to said receiver conversion means upon assertion of a loop back signal to the I/O interface circuit core, said converted input test data encoded with the alignment pattern;

d) a second switching means in electrical cooperation with said receiver converter stage having a first open position to permit receipt of externally transmitted data, and a second closed condition for receiving an input test data for reconversion, and alignment of the reconverted input test data to provide an output test data, and for halting receipt of the externally transmitted data upon assertion of the loop back signal to the I/O interface circuit core; and

e) an error analysis means for comparing said output test data with said input test data.

10. A loop back test system as in claim 9 wherein said I/O interface circuit core is a serializer/deserializer interface for converting alignment coded parallel formatted data to serial formatted data for transmission, and for converting serial formatted data to parallel formatted data for reception.

11. A loop back test system as in claim 9 further comprising an in-core built-in self-test (BIST) means for providing pseudo-random, alignment of encoded, said input test data to said transmitter input stage.

12. A loop back test system as in claim 11 wherein said error analysis means is disposed in the BIST means and includes an error counter and error trace buffer for determining and reporting the bit-error rate of the output test data as compared to the input test data.

13. A loop back test system as in claim 9 wherein said first data switching means includes semiconductor switching devices, said first data switching means being designed to maintain the direct current balance of the I/O interface circuit core.

14. A loop back test system as in claim 13 wherein said semiconductor switching devices are MOSFET transistors.

15. A loop back test system as in claim 9 wherein said second data switching means includes semiconductor switching devices, said second data switching means being designed to maintain the direct current balance of the I/O interface circuit core.

16. A loop back test system as in claim 15 wherein said semiconductor switching devices are MOSFET transistors.

17. A loop back test method for detection of intra-domain errors of an integrated I/O interface core of an integrated circuit, comprising the following steps in any operative order:

a) providing the integrated I/O interface core having both a transmitter section and a receiver section, said transmitter section comprising;

i) a transmitter input stage for receiving transmitter input data, said input data encoded with an alignment patter and said input data having a first format, and

ii) a transmitter converter stage for converting said input data into transmitter output data, said output data having a second format,

and said receiver section comprising;

iii) a receiver converter stage for receiving said transmitter output data for conversion of said output data to said first format to provide received reconverted data,

iv) a receiver alignment stage for decoding said alignment pattern from said received reconverted data, and for aligning said received reconverted data to conform to timing of said transmitter input data;

said transmitter input stage further comprising;

v) a first switching circuit in electrical cooperation with said transmitter input stage having a first open condition, and a second closed condition, said second closed condition for shunting transmitter input test data from said transmitter converter stage to said receiver converter stage to provide loop back data to said second receiver converter stage, said first switching circuit second closed condition being enabled upon assertion of a loop back signal to the I/O interface core, and

said receiver further comprising;

vi) a second switching circuit in electrical cooperation with said receiver converter stage having a first open position to permit receipt of externally transmitted data, and a second closed condition for receiving said loop back data for reconversion of said loop back data to said first format to provide output test data, and for halting receipt of said externally transmitted data, said second closed condition being enabled upon assertion of the loop back signal to the I/O interface core; and

an error analysis circuit for comparing said output test data with said input test data,

b) asserting a loop back test enable signal to the I/O interface core to enable said second closed condition of said first switching circuit, and to enable said second closed condition of said second switching circuit;

c) inputting said transmitter input data into said transmitter input stage, said input test data encoded with the alignment pattern;

d) converting said input test data in said transmitter converter stage from the first format to the second format;

e) shunting said input test data directly to a said receiver converter stage for conversion of said input test data from said second format to said first format;

f) decoding said alignment pattern from said input test data for alignment of said input test data;

g) aligning said input test data to provide aligned output test data; and

h) comparing said aligned output test data with said input test data.

18. A loop back test method as in claim 17 wherein said I/O interface core is a serializer/deserializer I/O interface core.

19. A loop back test method as in claim 17 wherein said step of asserting the loop back test enable signal is initiated off-chip via a loop back enable pin on the integrated circuit accessible off-chip.

20. A loop back test method as in claim 17 wherein said comparing step is performed by an in-core built-in self-test (BIST) circuit, said BIST circuit includes an error counter and error trace buffer for determining and reporting the bit-error rate of the output test data as compared to the input test data.