Remote identification of integrated circuit

• US 5,787,174 A
• Filed: 11/02/1995
• Issued: 07/28/1998
• Est. Priority Date: 06/17/1992
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, John R.
• Primary Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US08/556,818
• Time in Patent Office: 999 Days
• Field of Search: 380/4, 380/23, 380/25, 438/19, 324/764, 342/42, 342/44
• US Class Current: 713/189
• CPC Class Codes: G01S 13/758 using a signal generator powered by the interrogation signal
• CPC Class Codes: G01S 13/765 with exchange of information between interrogator and responder
• CPC Class Codes: G01S 13/767 Responders; Transponders teaching or practice apparatus for gun-aiming or gun-laying using reflecting targets or active targets F41G3/26
• CPC Class Codes: G01S 13/825 with exchange of information between interrogator and responder
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07767 the first and second communication means being two different antennas types, e.g. dipole and coil type, or two antennas of the same kind but operating at different frequencies
• CPC Class Codes: G06K 19/07786 the antenna being of the HF type, such as a dipole
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10049 binary tree
• CPC Class Codes: G06K 7/10356 using a plurality of antennas, e.g. configurations including means to resolve interference between the plurality of antennas
• CPC Class Codes: G07B 2017/00629 Circuit, e.g. transponder
• CPC Class Codes: H01Q 1/2225 used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 21/24 Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction circularly polarised patch antennas H01Q9/0428; circularly polarised horns H01Q13/0241; cross-polarised horns H01Q13/0258; polarisation converters H01Q15/242; cross-polarised rear feeds H01Q19/136; crossed polarisation dual antenna H01Q25/001
• CPC Class Codes: H01Q 9/28 Conical, cylindrical, cage, strip, gauze, or like elements having an extended radiating surface; Elements comprising two conical surfaces having collinear axes and adjacent apices and fed by two-conductor transmission lines waveguide horns or mouths H01Q13/00; slot antennas H01Q13/00
• CPC Class Codes: H01Q 9/285 Planar dipole H01Q9/065 takes precedence; patch antenna H01Q9/0407
• CPC Class Codes: H04L 2101/604 Address structures or formats
• CPC Class Codes: H04L 2101/622 Layer-2 addresses, e.g. medium access control [MAC] addresses
• CPC Class Codes: H04L 61/35 involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function
• CPC Class Codes: H04L 61/5038 : for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
• CPC Class Codes: H04L 61/5046 : Resolving address allocation conflicts; Testing of addresses testing when self-assigning an address H04L61/5092
• CPC Class Codes: H04L 61/5069 : for group communication, multicast communication or broadcast communication
• CPC Class Codes: H04L 61/5084 : Providing for device mobility network addressing or numbering for mobility support in wireless networks H04W8/26; mobile IP H04W80/04
• CPC Class Codes: H04L 61/5092 : by self-assignment, e.g. picking addresses at random and testing if they are already in use
• CPC Class Codes: H04L 63/0492 : by using a location-limited connection, e.g. near-field communication or limited proximity of entities
• CPC Class Codes: H04L 63/0823 : using certificates cryptographic mechanisms or cryptographic arrangements for entity authentication involving certificates H04L9/3263
• CPC Class Codes: H04W 8/26 : Network addressing or numbering for mobility support

Abstract

Circuitry mounted within a single hybrid or monolithic integrated circuit (I.C.) package including: (1) a first integrated circuit which is desired to be tracked for some purpose such as security or inventory, and (2) a second circuit having a memory for storing an identification number and an RF transceiver for transmitting the stored number in response to an RF interrogation signal. For security purposes, the invention makes it difficult or impossible for a thief to alter the identification number without destroying the LC., because the identification number is stored in memory within the I.C. For inventory purposes, the invention overcomes the need to affix an external identification tag to the I.C. package. The invention is especially suited for protecting a highly valuable first integrated circuit such as a microprocessor.

Claims

1. Integrated circuit apparatus incorporating an identification number, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package, wherein the first integrated circuit has a primary function different from radio frequency identification; and

a radio frequency identification circuit, mounted within the package, including

an ID number memory integrated circuit for storing an identification number, and

an integrated circuit RF transceiver including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal.

2. Apparatus according to claim 1, wherein:

a single, monolithic, integrated circuit die mounted within the package contains said first integrated circuit, said ID memory integrated circuit, and said integrated circuit RF transceiver; and

the package is a monolithic integrated circuit package.

3. Apparatus according to claim 1, wherein the package is a hybrid integrated circuit package.

9. Apparatus according to claim 1, wherein:

the first integrated circuit is fabricated on a first integrated circuit substrate area; and

the radio frequency identification circuit is fabricated on a second integrated circuit substrate area;

wherein the first area is substantially greater than the second area.

4. Integrated circuit apparatus incorporating an identification number, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package;

a re-writable memory integrated circuit for storing an identification number, including

a write enable input to which an electrical signal must be applied in order to re-write the number stored in the memory with a specific new value; and

an integrated circuit RF transceiver, mounted within the package, including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal;

wherein the integrated circuit package completely encapsulates the memory circuit so that the write enable input is not connected to any electrical contact external to the package.

5. Integrated circuit apparatus incorporating an identification number, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package;

a memory integrated circuit, mounted within the package, for storing an identification number;

means for storing in the memory an identification number which has a value which is one of a limited number of values which are valid according to a predetermined algorithm; and

an integrated circuit RF transceiver, mounted within the package, including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal.

10. Apparatus according to claim 5, wherein:

the identification number occupies a predetermined number of bits in the memory; and

the algorithm recognizes as valid identification numbers only a small fraction of all possible numbers having said predetermined number of bits.

6. Integrated circuit apparatus incorporating an identification number, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package;

a memory integrated circuit, mounted within the package, for storing an identification number;

an integrated circuit RF transceiver, mounted within the package, including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal and

a circuit for testing whether the identification number stored in the ID memory has a value which is one of a limited number of values which are valid according to a predetermined algorithm.

7. Apparatus according to claim 6, wherein the testing circuit further includes a circuit for disabling one or more operations of the first integrated circuit if the testing circuit indicates the stored identification number is invalid.

11. Apparatus according to claim 6, wherein the first integrated circuit includes the testing circuit.

12. Apparatus according to claim 6, further comprising:

a second circuit located outside the integrated circuit package;

wherein the second circuit is connected to the first integrated circuit; and

wherein the second circuit includes the testing circuit.

13. Apparatus according to claim 12, wherein:

the first integrated circuit is a microprocessor; and

the second circuit is a computer motherboard on which the integrated circuit package is mounted.

8. Apparatus for identifying a first integrated circuit, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package;

an ID number memory integrated circuit, mounted within the package, for storing an identification number, wherein the identification number stored in the ID memory has a value which is one of a limited number of values which are valid according to a predetermined algorithm;

an integrated circuit RF transceiver, mounted within the package, including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal; and

an interrogator RF transceiver, physically separate from and physically unattached to the integrated circuit package, including

an interrogator RF transmitter circuit for transmitting said RF interrogation signals, and

an interrogator RF receiver circuit for receiving said identification RF signals from the integrated circuit RF transceiver and for detecting whether the identification number conveyed in each identification RF signal has a valid value.

14. Integrated circuit apparatus incorporating an identification number, comprising:

an integrated circuit package;

a first integrated circuit mounted within the package;

a memory integrated circuit for storing an identification number;

an integrated circuit RF transceiver, mounted within the package, including

a receiver integrated circuit for receiving RF signals, and

a transmitter integrated circuit for transmitting an identification RF signal conveying the stored identification number after the receiver circuit receives an RF interrogation signal; and

a battery, connected to the memory circuit, which is mounted to the integrated circuit package in such a way that the battery cannot be disconnected from the memory circuit without physically defacing the integrated circuit package.

15. A method of identifying an integrated circuit, comprising the steps of:

providing an integrated circuit package;

mounting within the package a first integrated circuit which performs a primary function different from radio frequency identification;

mounting within the package a radio frequency identification circuit which includes a memory integrated circuit and an RF transceiver integrated circuit;

storing an identification number in the memory;

the RF transceiver receiving RF signals; and

upon receiving an RF interrogation signal, the RF transceiver transmitting an identification RF signal conveying the identification number stored in the memory.

16. A method according to claim 15, further comprising the steps of:

fabricating the first integrated circuit on a first integrated circuit substrate area; and

fabricating the radio frequency identification circuit on a second integrated circuit substrate area;

wherein the first area is substantially greater than the second area.

17. A method according to claim 15, further comprising the step of:

fabricating both the first integrated circuit and the radio frequency identification circuit on a single, monolithic, integrated circuit substrate;

wherein the step of providing an integrated circuit package comprises providing a monolithic integrated circuit package.

18. A method according to claim 17, wherein the fabricating step comprises

fabricating the first integrated circuit on a first area of the single substrate;

and

fabricating the radio frequency identification circuit on a second area of the single substrate;

wherein the first area is substantially greater than the second area.

19. A method of identifying an integrated circuit, comprising the steps of:

providing an integrated circuit package;

mounting within the package a first integrated circuit;

mounting within the package an RF transceiver integrated circuit;

mounting within the package a re-writable memory integrated circuit for storing an identification number, wherein the memory circuit includes a write enable input to which an electrical signal must be applied in order to re-write the number stored in the memory with a specific new value;

encapsulating the memory circuit within the package so that the write enable input is not connected to any electrical contact external to the package;

the RF transceiver receiving RF signals; and

upon receiving an RF interrogation signal, the RF transceiver transmitting an identification RF signal conveying the identification number stored in the memory.

20. A method of identifying an integrated circuit, comprising the steps of:

providing an integrated circuit package;

mounting within the package a first integrated circuit;

mounting within the package an RF transceiver integrated circuit;

mounting within the package a memory integrated circuit;

storing in the memory an identification number having a value which is one of a limited number of values which are valid according to a predetermined algorithm;

the RF transceiver receiving RF signals; and

upon receiving an RF interrogation signal, the RF transceiver transmitting an identification RF signal conveying the identification number stored in the memory.

21. A method according to claim 20, wherein the storing step comprises:

storing in the memory the identification number having a predetermined number of bits;

wherein the algorithm recognizes as valid identification numbers only a small fraction of all possible numbers having said predetermined number of bits.

22. A method of identifying an integrated circuit, comprising the steps of:

providing an integrated circuit package;

mounting within the package a first integrated circuit;

mounting within the package an RF transceiver integrated circuit;

mounting within the package a memory integrated circuit;

storing in the memory an identification number;

the RF transceiver receiving RF signals;

upon receiving an RF interrogation signal, the RF transceiver transmitting an identification RF signal conveying the identification number stored in the memory; and

testing whether the identification number stored in the memory has a value which is one of a limited number of values which are valid according to a predetermined algorithm.

23. A method according to claim 22, further comprising the step of:

disabling one or more operations of the first integrated circuit if the testing step determines that the stored identification number has an invalid value.

24. A method according to claim 22, further comprising the steps of:

providing an interrogator RF transceiver which is physically separate from and physically unattached to the integrated circuit package;

the interrogator transceiver transmitting said RF interrogation signal; and

the interrogator transceiver receiving said identification RF signal from the integrated circuit RF transceiver;

wherein the step of testing whether the identification number stored in the memory has a valid value includes

the interrogator transceiver testing whether the identification number conveyed in the received identification RF signal has a valid value.