Method and apparatus for pattern recognition of wafer test bins

• US 5,787,190 A
• Filed: 06/27/1997
• Issued: 07/28/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Peng, Yeng-Kaung, Ho, Siu-May, Shiau, Ying
• Primary Examiner(s): Mancuso, Joseph
• Assistant Examiner(s): Werner, Brian P.
• Application Number:
  US08/884,316
• Time in Patent Office: 396 Days
• Field of Search: 438/5, 438/6, 438/7, 438/8, 438/9, 438/10, 438/11, 438/12, 438/13, 438/14, 438/15, 438/16, 438/17, 438/18, 438/141, 438/142, 382/148, 382/149, 382/227, 382/225, 382/159, 382/160, 382/144, 382/145, 364/490
• US Class Current: 382/145
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.

Claims

1. A wafer test bin pattern recognition system for a fabrication facility for manufacturing a plurality of semiconductor wafers having plural circuit patterns formed as dice thereon, the system comprising:

a neural network processor linked to said fabrication facility for classifying a population of a plurality of fabricated semiconductor wafers by an identification code which denotes a particular fault for each non-functional die on the plurality of wafers for generating a first wafer map for the population of wafers indicating at least one fault pattern;

a semiconductor tester disposed to receive said plurality of wafers to generate a fault pattern for each of the plurality of wafers on a second wafer map for each wafer; and

a data analyzer for correlating said fault pattern on said first wafer map with said fault patterns on each of said second wafer maps for producing a confirmed fault pattern indicative of corrections required in said fabrication facility.

2. A wafer test bin pattern recognition system for operation with a fabrication facility for manufacturing a plurality of semiconductor wafers, the system comprising:

a wafer tester linked to said fabrication facility to receive a population of a plurality of wafers for providing test data for each die and for identifying each of non-functional die on each of said plurality of wafers by an identifying code that represents a type of fault

a processor including a neural network coupled to said wafer tester for processing the test data on the dice on each of the plurality of wafers in the population of wafers to generate a first wafer map of non-functional dice at wafer coordinates detected for each wafer;

a first analyzer coupled to receive the test data for each die to generate a second wafer map for each wafer of the population of wafers;

a second analyzer for analyzing fault patterns on said first wafer map overlapping fault patterns on each of said second wafer maps; and

a data analyzer coupled to said second analyzer for producing an output indication of a confirmed fault pattern requiring correction of a process in said fabrication facility for manufacturing a subsequent population of wafers.

3. A method for operation of a wafer tester and neural network for selecting defect patterns in a population of fabricated semiconductor wafers from test data on dice on each wafer of the population as an indication of required fabrication corrections, the method comprising:

generating from the wafer tester a set of test data that contains a bin summary of a plurality of functional and non-functional dice on each wafer of the population of fabricated wafers, with each fault of a non-functional die being assigned a code designating the type of fault which said code represents;

forming a first wafer map for each wafer of the population of fabricated wafers from the set of test data generated from the wafer tester;

supplying the bin summaries for the population of fabricated wafers to the neural network to generate a representative wafer map including a pattern of a type of fault in non-functional dice on the population of fabricated wafers;

comparing the first map for each wafer with the representative wafer map from the population of fabricated wafers for a type of fault pattern; and

selecting for a wafer a fault pattern in a first map overlapping with a pattern of a type of fault in the representative wafer map as an indication of fault for correction in subsequent fabrication of a population of wafers.