Wiring pattern inspection apparatus for printed circuit board

• US 5,787,191 A
• Filed: 06/06/1995
• Issued: 07/28/1998
• Est. Priority Date: 02/26/1991
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kawamura, Hideaki, Kawakami, Hidehiko, Maruyama, Yuji, Kondoh, Katsuhiro, Ichikawa, Iwao, Yamamoto, Atsuharu
• Primary Examiner(s): Boudreau, Leo
• Assistant Examiner(s): Davis, Monica S.
• Application Number:
  US08/467,442
• Time in Patent Office: 1,148 Days
• Field of Search: 382/149, 382/256, 382/257
• US Class Current: 382/149
• CPC Class Codes: G01R 31/309 of printed or hybrid circuits or circuit substrates
• CPC Class Codes: G06T 2207/20044 Skeletonization; Medial axis transform
• CPC Class Codes: G06T 2207/30141 Printed circuit board [PCB]
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/194 involving foreground-background segmentation

Abstract

A wiring pattern inspection apparatus for inspecting an abnormality of a wiring pattern formed on a printed circuit board, which is equipped with an optical image pickup device for optically illuminating a surface of the printed circuit board including the wiring pattern to photoelectrically convert optical information of the printed circuit board surface due to the optical illumination into a grey level image. This grey level image is converted into a bi-level image which separates the grey level image into the wiring pattern side and a background side of the wiring pattern. Thereafter, the bi-level image is once contracted by a first size and then expanded by a second size so as to eliminate a micro conductive portion left on the printed circuit board or a micro pinhole which can be disregarded in the abnormality inspection, thereby preventing the excessive detection.

Claims

1. A wiring pattern inspection apparatus for inspecting an abnormality of wiring pattern formed on a printed circuit board, comprising:

image inputting means for optically illuminating a surface of said printed circuit board including said wiring pattern and for photoelectrically converting optical information of said printed circuit board surface due to the optical illumination into a grey level image;

bi-level conversion means responsive to said grey level image from said image inputting means to convert said grey level image into a bi-level image in which the wiring pattern side and a background side of said wiring pattern are separated from each other;

first removing means coupled to said bi-level conversion means to contract said bi-level image by a size corresponding to n pixels from the background side and then to expand the contracted bi-level image by a size corresponding to m pixels, wherein said first removing means includes a first AND-processing means to calculate a logical product of the expanded bi-level image and said bi-level image from said bi-level conversion means;

second removing means coupled to said first removing means to invert the logical-product bi-level image which is the calculation result of said first removing means and then to contract the inverted logical-product bi-level image by a size corresponding to n'"'"' pixels and further, to expand the contracted inverted logical-product bi-level image by a size corresponding to m'"'"' pixels, wherein said second removing means includes,

a second AND-processing means to calculate a logical-product of the expanded inverted logical-product bi-level image and the inverted logical-product bi-level image, and

an inverter means to again invert the calculation result of said second AND-processing means; and

defect detecting means coupled to said second removing means to detect a defect of said wiring pattern on the basis of the inverted calculation result of said inverter means.