Improving memory layout based on connectivity considerations

• US 5,787,284 A
• Filed: 10/07/1996
• Issued: 07/28/1998
• Est. Priority Date: 12/28/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Donawa, Christopher Michael, McInnes, James Lawrence, Blainey, Robert James
• Primary Examiner(s): Cosimano, Edward R.
• Assistant Examiner(s): Nguyen, Cuong H.
• Application Number:
  US08/726,038
• Time in Patent Office: 659 Days
• Field of Search: 395/705, 395/707, 395/708, 395/709, 395/701
• US Class Current: 717/144
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 9/44557 Code layout in executable memory

Abstract

A technique used during interprocedural compilation in which program objects are grouped together based on the weights of the connections between the objects and their costs. System-imposed constraints on memory size can be taken into account to avoid creating groupings that overload the system'"'"'s capacity. The groupings can be distributed over memories located on different processors.

Claims

1. A method for optimizing a memory layout of program objects, comprising the computer implemented steps of:

weighting the access connections between the program objects and determining the cost of the program objects during complication;

building aggregates of the program objects for larger weighted connections before smaller weighted connections, limited by a maximum aggregate cost; and

generating code to map the groups to memory;

whereby the code optimizes the memory layout of the program objects.

2. A method according to claim 1 wherein the step of generating code comprises generating code to map the groups to distributed memories.

3. A method for optimizing memory layout following complication, comprising the computer-implemented steps of:

defining a limit;

identifying a referenced program object;

building a weighted graph wherein weights on nodes represent program object size and weights on edges represent access relationships between nodes;

grouping the heaviest edges together from the weighted interference graph while the total weight of the nodes does not meet the limit; and

remapping the program objects based on the grouping;

the remapping producing an optimized memory layout of the program objects.

4. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps of optimizing memory layout following complication, said method steps comprising:

defining a limit;

identifying a referenced program object;

building a weighted graph wherein weights on nodes represent program object size and weights on edges represent access relationships between nodes;

grouping the heaviest edges together from the weighted interference graph while the total weight of the nodes does not meet a preset limit; and

remapping the program objects based on the grouping.