Computer incorporating a power supply control system therein

• US 5,787,293 A
• Filed: 11/14/1996
• Issued: 07/28/1998
• Est. Priority Date: 04/24/1996
• Status: Expired due to Fees

• Current Assignee: Daewoo Electronics (Government of South Korea)
• Original Assignee: Daewoo Electronics (Government of South Korea)
• Inventors: Kim, Ki-Hong, Ham, Seong-Sik, Choi, Chang-Hun, Hong, Jean-Gee
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Myers, Paul R.
• Application Number:
  US08/749,027
• Time in Patent Office: 621 Days
• Field of Search: 395/750.01-750.08, 395/651, 395/652, 395/284, 395/182.22
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A computer incorporates therein a control system for efficiently turning on and off a power supply on and off therein to control on-off operations of the computer. In the control system, a power detection signal is derived first based on a power selection signal generated when a power on/off key of the computer is actuated to control the on-off operations of the computer at a signal detector. And then, at a first generator, a first power control signal and a selection control signal are obtained from the derived power detection signal in response to a first mode control signal. Next, a second power control signal is derived from the power detection signal, the selection control signal and a second mode control signal at a second generator. Finally, the first and the second power control signals are logically combined at a second logic circuit to generate and provide a definitive power control signal to the power supply, thereby selectively supplying DC output voltages to designated components of the computer to control the on-off operations of the computer.

Claims

1. A computer incorporating therein a control system for controlling the operation of a power supply therein which supplies a plurality of DC output voltages to designated components of the computer to control on-off operations of the computer, wherein the control system comprises:

means for detecting a power selection signal, generated when a power on/off key of the computer is actuated to control the on-off operations of the computer, to provide a detected power selection signal as a power detection signal;

means for producing a first, a second and a third mode control signals when predetermined instructions corresponding to the signals are given by the computer user, respectively;

a first generation means, responsive to the first mode control signal, for generating a first power control signal and a selection control signal by using the power detection signal;

a second generation means, responsive to the selection control signal and the second and the third mode control signals, for generating a second power control signal by utilizing the power detection signal; and

a combining means for logically combining the first and the second power control signals to generate a definitive power control signal and to provide it to the power supply, thereby selectively supplying the DC output voltages to the designated components of the computer to control the on-off operations of the computer.

2. The computer of claim 1, wherein the second generation means includes:

a first checking means for checking whether or not the power detection signal is in a first logic state indicating that the power on/off key has been actuated to initialize the operation of the computer when it is off; and

for generating, if the power detection signal is in the first logic state, the second power control signal of the first logic state;

a second checking means for checking whether or not the power detection signal is in a second logic state indicating that the power on/off key has been actuated to halt the operation of the computer when it is running, and for selectively producing, if the power detection signal is in the second logic state, the second power control signal of the first logic or the second logic state in response to the selection control signal and the second and the third mode control signals; and

means for coupling the power detection signal to the first checking means when the computer is off and, in response to the selection control signal, for selectively coupling the power detection signal to the second checking means when the computer is on.

3. The computer of claim 2, wherein the second checking means includes:

means for retrieving, if the power detection signal is in the second logic state, predetermined guide information from a memory of the computer to display the retrieved predetermined guide information;

means, in response to the second mode control signal provided after the display of the predetermined guide information, for generating the second power control signal of the first logic state to halt the operation of the computer; and

means, in response to the third mode control signal provided after the display of the predetermined guide information, for generating the second power control signal of the second logic state to continue the operation of the computer.

4. The computer of claim 2, wherein each of the first, second and third mode control signals includes an address and a data signals.

5. The computer of claim 3, wherein the first generation means includes:

a latching means, in response to the address signal of the first mode control signal, for latching the data signal thereof to produce the selection control signal; and

means, in response to the selection control signal, for selectively generating the first power control signal of the first or the second logic state by using the power detection signal.

6. The computer of claim 2, wherein the combining means is operated by employing an AND gate.

7. The computer of claim 5, wherein the latching means is operated by utilizing a D flip/flop.

8. The computer of claim 7, wherein the first generation means further includes means for generating and providing a clock signal by using the address signal to a clock input of the D flip/flop.

9. The computer of claim 8, wherein said means for generating and providing the clock signal is operated by utilizing a programmable array logic.

10. The computer of claim 1, wherein the power selection signal is generated when a power on/off key on a remote controller of the computer is actuated to control the on-off operations of the computer.

11. A computer incorporating therein a control system for controlling the operation of a power supply therein which supplies a plurality of DC output voltages to designated components of the computer to control on-off operations of the computer, wherein the control system comprises:

a first detection means for detecting a first power selection signal, generated when a power on/off key of the computer is actuated to control the on-off operations of the computer, to provide a first detected power selection signal;

a second detection means for detecting a ringing signal, generated when a user of any one of remotely located communications terminals calls a receiving communications terminal coupled with the computer to initialize the operation of the computer, to produce a detected ringing signal;

means for producing a first, a second, a third and a fourth mode control signals when corresponding predetermined instructions are given by the computer user, respectively;

a first generation means, responsive to the first mode control signal, for generating a second power selection signal by using the detected ringing signal;

a first combining means for logically combining the first detected power selection signal and the second generated power selection signal to produce a power detection signal;

a second generation means, responsive to the second mode control signal, for generating a first power control signal and a selection control signal by employing the power detection signal;

a third generation means, responsive to the selection control signal and the third and the fourth mode control signals, for generating a second power control signal by using the power detection signal; and

a second combining means for logically combining the first and the second power control signals to generate and provide a definitive power control signal to the power supply, thereby selectively supplying the DC output voltages to the designated components of the computer to control the on-off operations of the computer.

12. The computer of claim 11, wherein the first generation means includes:

means for generating, if a ringing signal is detected when the computer is off, the third power selection signal of a first logic state in response to the first mode control signal; and

means for generating, if ringing signals following the first are detected when the computer is on, the third power selection signal of a second logic state in response to the second power control signal.

13. The computer of claim 12, wherein the third generation means includes:

a first checking means for checking whether or not the power detection signal is in a first logic state indicating that the power on/off key has been actuated or a ringing signal has been detected to initialize the operation of the computer when it is off; and

for generating, if the power detection signal is in the first logic state, the second power control signal of the first logic state;

a second checking means for checking whether or not the power detection signal is in a second logic state indicating that the power on/off key has been actuated to halt the operation of the computer when it is on, and for selectively producing, if the power detection signal is in the second logic state, the second power control signal of the first logic or the second logic state in response to the selection control signal and the third and the fourth mode control signals; and

means for coupling the power detection signal to the first checking means when the computer is off and, in response to the selection control signal, for selectively coupling the power detection signal to the second checking means when the computer is on.

14. The computer of claim 13, wherein the second checking means includes:

means for retrieving, if the power detection signal is in the second logic state, predetermined guide information from a memory of the computer to display the retrieved predetermined guide information;

means, in response to the third mode control signal provided after the display of the predetermined guide information, for generating the second power control signal of the first logic state to halt the operation of the computer; and

means, in response to the fourth mode control signal provided after the display of the predetermined guide information, for generating the second power control signal of the second logic state to continue the operation of the computer.

15. The computer of claim 14, wherein said second checking means further includes:

means for generating, if any of voice messages and data is inputted from any one of the remotely located communications terminals thereto when the computer is on, the second power control signal of the first logic state to continue the operation of the computer; and

means for generating, if no information is inputted from any one of the remotely located communications terminals thereto for a predetermined time period, the second power control signal of the second logic state to halt the operation of the computer.

16. The computer of claim 12, wherein each of the first, second, third and fourth mode control signals includes an address and a data signals.

17. The computer of claim 16, wherein the second generation means includes:

a latching means for latching, in response to the address signal of the second mode control signal, the data signal thereof to produce the selection control signal; and

means, in response to the selection control signal, for generating the first power control signal by utilizing the power detection signal.

18. The computer of claim 17, wherein the latching means is operated by utilizing a D flip/flop.

19. The computer of claim 17, wherein the second generation means further includes means for generating a clock signal by using the address signal and providing it to a clock input of the D flip/flop.

20. The computer of claim 19, wherein said means for generating and providing the clock signal is operated by utilizing a programmable array logic.

21. The computer of claim 12, wherein the second detection means is operated by using a photocoupler.

22. The computer of claim 12, wherein the first combining means is operated by using an AND gate.

23. The computer of claim 12, wherein the second combining means is operated by employing an AND gate.

24. The computer of claim 11, wherein the first power selection signal is generated when a power on/off key on a remote controller of the computer is actuated to control the on-off operations of the computer.