Bus interface circuit for an intelligent low power serial bus

• US 5,787,298 A
• Filed: 08/18/1995
• Issued: 07/28/1998
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: General Magic, Inc.
• Inventors: Broedner, Walter F., Faddell, Anthony M.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/516,849
• Time in Patent Office: 1,075 Days
• Field of Search: 395/653, 395/284, 395/281, 395/750, 395/309, 395/285
• US Class Current: 713/323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Abstract

A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a first bidirectional signal line, a second bidirectional signal line coupled to the bus clock and data lines, respectively, and an interface circuit coupled to the first and second bidirectional signal lines. The interface circuit includes a first buffer circuit coupled to the first and second bidirectional signal lines, and a second buffer circuit coupled to the first buffer circuit. A control circuit in the interface circuit couples the first and second buffer circuits where in a first mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first and second buffer circuits, and in a second mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first buffer circuit and configures the second buffer circuit to terminate the first bidirectional signal line. Thus bus power supply line is coupled to the interface circuit and a voltage on the power supply line is used to power the first and second buffer circuits and the control circuit. The bus interrupt line is coupled to the control circuit of the interface circuit. The interface circuit is also coupled to signal lines of the peripheral device.

Claims

1. A method of operation of a serial bus interface circuit in a peripheral device comprising:

entering a power-on state upon detection of a transmission error over a bus coupled to said bus interface circuit; and

entering said power-on state upon powering-up said peripheral device wherein said bus interface circuit generates an interrupt signal upon entering said power-on state.

2. A method of operation of a serial bus interface circuit in a peripheral device as in claim 1 further comprising:

transitioning from said power-on state to a no-address state upon receipt over said bus of a start of transmission command addressed to said peripheral device.

3. A method of operation of a serial bus interface circuit in a peripheral device as in claim 2 further comprising:

transitioning from said no-address state to a last-idle state upon receipt over said bus of an assign address command addressed to said peripheral device.

4. A method of operation of a serial bus interface circuit in a peripheral device as in claim 3 further comprising:

transitioning from said last-idle state to a mid-idle state upon receipt over said bus of an assign mid-peripheral command addressed to said peripheral device.

5. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a last-idle state upon receipt over said bus of an assign last-peripheral command addressed to said peripheral device.

6. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said last-idle state to a pre get state upon receipt over said bus of a get command addressed to said peripheral device when said peripheral device is a first peripheral device on said bus.

7. A method of operation of a serial bus interface circuit in a peripheral device as in claim 6 further comprising:

transitioning from said pre get state to a get state upon receipt over said bus of a start of transmission command from said peripheral device.

8. A method of operation of a serial bus interface circuit in a peripheral device as in claim 7 further comprising:

transitioning from said get state to a post get state upon receipt over said bus of an end of transmission command from said peripheral device.

9. A method of operation of a serial bus interface circuit in a peripheral device as in claim 8 further comprising:

transitioning from said post get state to said last-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.

10. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a pre get state upon receipt over said bus of a get command addressed to said peripheral device when said peripheral device is a first peripheral device on said bus.

11. A method of operation of a serial bus interface circuit in a peripheral device as in claim 10 further comprising:

transitioning from said pre get state to a get state upon receipt over said bus of a start of transmission command from said peripheral device.

12. A method of operation of a serial bus interface circuit in a peripheral device as in claim 11 further comprising:

transitioning from said get state to a post get state upon receipt over said bus of an end of transmission command from said peripheral device.

13. A method of operation of a serial bus interface circuit in a peripheral device as in claim 12 further comprising:

transitioning from said post get state to said mid-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.

14. A method of operation of a serial bus interface circuit in a peripheral device as in claim 3 further comprising:

transitioning from said last-idle state to a get state upon receipt over said bus of a get command addressed to said peripheral device when said peripheral device is other than a first peripheral device on said bus.

15. A method of operation of a serial bus interface circuit in a peripheral device as in claim 14 further comprising:

transitioning from said get state to a post get state upon receipt over said bus of an end of transmission command from said peripheral device.

16. A method of operation of a serial bus interface circuit in a peripheral device as in claim 15 further comprising:

transitioning from said post get state to said last-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.

17. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a get state upon receipt over said bus of a get command addressed to said peripheral device when said peripheral device is other than a first peripheral device on said bus.

18. A method of operation of a serial bus interface circuit in a peripheral device as in claim 17 further comprising:

transitioning from said get state to a post get state upon receipt over said bus of an end of transmission command from said peripheral device.

19. A method of operation of a serial bus interface circuit in a peripheral device as in claim 18 further comprising:

transitioning from said post get state to said mid-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.

20. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a pre pass up state upon receipt over said bus of a get command addressed to another peripheral device on said bus downstream from said peripheral device when said peripheral device is a first peripheral device on said bus.

21. A method of operation of a serial bus interface circuit in a peripheral device as in claim 20 further comprising:

transitioning from said pre pass up state to a pass up state upon receipt over said bus of a start of transmission command from said another peripheral device.

22. A method of operation of a serial bus interface circuit in a peripheral device as in claim 21 further comprising:

transitioning from said pass up state to said mid-idle state upon receipt over said bus of an end of transmission command from said another peripheral device.

23. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a pass up state upon receipt over said bus of a get command addressed to another peripheral device on said bus downstream from said peripheral device when said peripheral device is other than a first peripheral device on said bus.

24. A method of operation of a serial bus interface circuit in a peripheral device as in claim 23 further comprising:

transitioning from said pass up state to said mid-idle state upon receipt over said bus of an end of transmission command from said another peripheral device.

25. A method of operation of a serial bus interface circuit in a peripheral device as in claim 3 further comprising:

transitioning from said last-idle state to a send state upon receipt over said bus of a send command addressed to said peripheral device.

26. A method of operation of a serial bus interface circuit in a peripheral device as in claim 25 further comprising:

transitioning from said send state to said last-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.

27. A method of operation of a serial bus interface circuit in a peripheral device as in claim 4 further comprising:

transitioning from said mid-idle state to a send state upon receipt over said bus of a send command addressed to said peripheral device.

28. A method of operation of a serial bus interface circuit in a peripheral device as in claim 27 further comprising:

transitioning from said send state to said last-idle state upon receipt over said bus of an end of transmission command to said peripheral device from a bus dispatch.