Pin selection system for microcontroller having multiplexer selects between address/data signals and special signals produced by special function device

• US 5,787,299 A
• Filed: 11/18/1996
• Issued: 07/28/1998
• Est. Priority Date: 09/16/1994
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Khan, Ata R., Ostler, Farrell L., Goodhue, Gregory K.
• Primary Examiner(s): Meky, Moustafa M.
• Application Number:
  US08/751,281
• Time in Patent Office: 617 Days
• Field of Search: 395/821, 395/800, 395/500, 395/822, 395/823, 395/824, 395/827, 395/830, 326/37, 326/38, 326/41
• US Class Current: 712/39
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio

Abstract

A microcontroller with selectable function external pins. Program controllable configuration registers control pin function selection through multiplexers which select between data/address lines and special function unit output lines and which control line drivers which are disabled when the pins are used as input pins.

Claims

1. A pin function selection circuit for a microcontroller, comprising:

a configuration register having contents, said configuration register comprising an output configuration register and an input configuration register indicating a function of external pins of the microcontroller; and

a function selection circuit connected to the configuration register, to the external pins and to microcontroller units using different input/output function signals, said function selection circuit comprising;

a multiplex circuit connected to said output configuration register and the microcontroller units; and

a driver circuit connected to said input configuration register, said multiplex circuit, said microcontroller units and the external pins,

said multiplex circuit comprising;

bit multiplexers connected to the microcontroller units and the driver circuit; and

a decode unit connected to the output configuration register and the bit multiplexers.

2. A pin function selection circuit as recited in claim 1, wherein a configuration of the external pins is program controlled.

3. An external pin selection system for external pins of a single chip microcontroller, comprising:

a bus interface unit providing address/data signals over an external bus;

an output configuration register having contents programmable by the microcontroller;

an input configuration register having contents programmable by the microcontroller;

a special function device controllable by the microcontroller producing special function output signals and receiving special function input signals;

an output decode unit connected to said output configuration register and producing an output selection signal responsive to contents of said output configuration register;

a multiplexer connected to said output decode unit, said bus interface unit and said special function device, and selecting between the address/data signals and the special function output signals responsive to the output selection signal;

an input decode unit connected to said input configuration register and producing an input selection signal responsive to the contents of said input configuration register;

a line driver circuit connected to said input decode unit, the external pins and said multiplexer, and providing signals from said multiplexer responsive to the input selection signal; and

a data buffer connected between the external pins and said special function device and buffering the special function input signals.

4. An external pin selection system as recited in claim 3, wherein a configuration of said external pins is program controlled.

5. A pin function selection circuit as recited in claim 4, wherein said external bus has a programmable address bus width.

6. An external pin selection system as recited in claim 3, wherein said external bus has a programmable address bus width.

7. An external pin selection system for external pins of a single chip microcontroller, comprising:

a bus interface unit providing address/data signals over an external bus, said external bus having a programmable address bus width;

a configuration register having contents programmable by the microcontroller;

a special function device controllable by the microcontroller producing special function output signals and receiving special function input signals;

a decode unit connected to said configuration register and producing an output selection signal and an input selection signal in response to contents of said configuration register;

a multiplexer connected to said decode unit, said bus interface unit and said special function device, and selecting between the address/data signals and the special function output signals responsive to the output selection signal;

a line driver circuit connected to said input decode unit, the external pins and said multiplexer, and providing signals from said multiplexer responsive to the input selection signal; and

a data buffer connected between the external pins and said special function device and buffering the special function input signals.