Content addressable memory of a simple construction capable of retrieving a variable word length data

• US 5,787,458 A
• Filed: 09/03/1996
• Issued: 07/28/1998
• Est. Priority Date: 08/31/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Miwa, Tohru
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/706,470
• Time in Patent Office: 693 Days
• Field of Search: 711/108, 365/49, 395/306, 395/886
• US Class Current: 711/108
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A content addressable memory system includes one retrieval sense amplifier provided in common with a plurality of memory words. A logic operation between a result of retrieval outputted from the sense amplifier and the result of a preceding retrieval stored in a one-bit working register provided for the same sense amplifier is carried out by a control gate also provided for the same sense amplifier, and the result of the logic operation is stored back in the same working register. A plurality of working registers may be provided for each control gate and sense amplifier. The content addressable memory system can retrieve a variable word length data and can be realized with a reduced circuit area.

Claims

1. A content addressable memory comprising:

a memory array composed of a number of memory words divided into a plurality of logical address memory blocks;

a plurality of retrieval sense amplifiers, each provided in common to a plurality of memory words of the same number as the number of said logical address memory blocks so hat said plurality of memory words are included, one in one, in said plurality of logical address memory blocks, respectively, and each of said logical address blocks is constituted of only a memory word of the logical address of the same rank within said plurality of memory words in common to each one of said plurality of retrieval sense amplifiers;

a plurality of hold means, each provided for a corresponding one of the retrieval sense amplifiers, for holding the result of retrieval outputted from the corresponding retrieval sense amplifier;

a plurality of logic operations processing means, each having a first input connected to an output of a corresponding one of said retrieval sense amplifiers, a second input connected to an output of a corresponding one of said hold means, and an output connected to an input of the corresponding hold means, each of said logical operation processing means executing a logic operation between the result of retrieval held in the corresponding hold means and the result of retrieval outputted from the corresponding retrieval sense amplifier, and the result of said logic operations being stored back in said corresponding hold means,

the content addressable memory being so controlled that, when a retrieval is conducted, all the memory words included in a selected one of said plurality of logical address memory blocks are retrieved concurrently for the same retrieval data by means of the retrieval sense amplifiers, and said logic operation between the result of current retrieval outputted from each of said retrieval sense amplifiers and the result of the preceding retrieval held in the corresponding hold means is executed by the corresponding logic operation processing means, and the result of the logic operation executed is stored back in the same corresponding hold means.

2. A content addressable memory claimed in claim 1 wherein when a retrieval of a retrieval data having a data length longer than that of one memory word is conducted, the content addressable memory is so controlled that, all the memory words included in a first memory block of said plurality of logical address memory blocks are retrieved concurrently for a first retrieval data portion of the retrieval data by means of said retrieval sense amplifiers, and the retrieval result of said first retrieval data portion is stored in the plurality of hold means corresponding to each of said retrieval sense amplifiers, and then, all the memory words included in a second memory block of said plurality of logical address memory blocks including a memory word continuous in a logical address to each of the memory words included in said first memory block, are retrieved concurrently for a second retrieval data portion of the retrieval data continuous to said first retrieval data portion, by means of said retrieval sense amplifiers, and a logical conjunction (AND) operation between the current retrieval result of said second retrieval data portion outputted from each of said retrieval sense amplifiers and the preceding retrieval result of said first retrieval data portion held in the corresponding hold means is executed by the corresponding logic operation processing means, and the result of the logical operation executed is stored back in the same corresponding hold means, whereby the result of the retrieval of the retrieval data having a data word length extending over two memory words is obtained from each of said plurality of hold means.

3. A content addressable memory claimed in claim 1 wherein each of said retrieval sense amplifiers has an output connected to one input of a plurality of inputs of a corresponding logic operation processing means, and wherein for each of said retrieval sense amplifiers, there is a plurality of hold means each having an output connected to a corresponding one of the other inputs of said plurality of inputs of said corresponding logic operation processing means.

4. A content addressable memory claimed in claim 1 wherein all of said logic operation processing means are controlled to execute the same predetermined logic operation.

5. A content addressable memory claimed in claim 1 wherein each of said logic operation processing means is constituted of a control gate, and each of said hold means is constituted of a one-bit working register.

6. A content addressable memory claimed in claim 1 wherein each of said hold means is constituted of a memory circuit composed of a pair of inverters each having an input connected to an output of the other inverter, and

wherein each of said logic operation processing means includes two three-input selectors each receiving the output of a corresponding retrieval sense amplifier, an inverted value of the output of the corresponding retrieval sense amplifier, and a predetermined fixed logical value, and two switching transistors having control inputs connected to outputs of said two three-input selectors, respectively, one of said switching transistors being connected between an input of said memory circuit and a fixed voltage, and the other of said switching transistors being connected between an output of said memory circuit and said fixed voltage.

7. A content addressable memory claimed in claim 6 wherein each of said two switching transistors is a metal oxide semiconductor (MOS) transistor.