Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation

• US 5,787,479 A
• Filed: 04/29/1996
• Issued: 07/28/1998
• Est. Priority Date: 04/29/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: International Business Machines Corporation, Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Jessani, Romesh Mangho, Mallick, Soummya, Patel, Rajesh Bhikhubhai, Kuttanna, Belliappa Manavattira
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/639,576
• Time in Patent Office: 820 Days
• Field of Search: 711/125, 711/128, 711/133, 711/144, 711/145, 711/166, 711/167, 365/49, 395/185.07, 395/185.09
• US Class Current: 711/144
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

Claims

1. A method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation, said method comprising the steps of:

providing a tag in association with each cache line of said cache memory;

validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and

in response to an occurrence of a bus error during said linefill operation, invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, such that the integrity of information within said particular cache line is maintained.

2. The method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation according to claim 1, wherein said validating step is performed by setting a valid bit of said cache memory to a logical "1."

3. The method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation according to claim 1, wherein said invalidating step is performed by setting a valid bit of said cache memory to a logical "0."

4. The method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation according to claim 1, wherein said providing a tag step further comprises the step of providing a tag from an address.

5. A cache memory having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation, said cache memory comprising:

a plurality of cache lines having a tag associated with each of said plurality of caches lines;

means for validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and

means for invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, in response to an occurrence of a bus error during said linefill operation.

6. The cache memory having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation according to claim 5, wherein said validating means sets a valid bit of said cache line to a logical "1" to indicate said particular cache line is valid.

7. The cache memory having a mechanism for preventing information corruption due to a bus error which occurs during a cache memory operation according to claim 5, wherein said invalidating means sets a valid bit of said cache line to a logical "0" to indicate said particular cache line is invalid.

8. The cache memory having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation according to claim 5, wherein said cache memory is a two way instruction cache.

9. A data processing system having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation, said data processing system comprising:

a processor;

a cache memory within said processor, wherein said cache memory includes a plurality of cache lines having a tag associated with each of said plurality of cache lines;

means for validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and

means for invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, in response to an occurrence of a bus error during said linefill operation.

10. The data processing having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation according to claim 9, wherein said validating means sets a valid bit of said cache line to a logical "1" to indicate said particular cache line is valid.

11. The data processing having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation according to claim 9, wherein said invalidating means sets a valid bit of said cache line to a logical "0" to indicate said particular cache line is invalid.