High-speed data communications modem
First Claim
1. A parallel processing system for a high speed data communications modem, comprising:
- a. a first state machine controlled device that performs a first data communication function;
b. a first register set addressable by said first device;
c. a second state machine controlled device that performs a second data communication function;
d. a second register set addressable by said second device;
e. a microprocessor connected to said first and second register sets;
f. a shared memory;
g. a memory access arbitration unit connected to said first and second devices and to said shared memory, and operable to accept a memory access request from each of said first and second devices during each clock cycle of the parallel processing system and to access said shared memory in response to said memory access requests and;
h. a register file connected to said microprocessor and to said first and second devices, said register file containing a pointer to an area of said shared memory for storing data associated with said first data communication function and a pointer to an area of said shared memory for storing data associated with said second data communication function, said first and second pointers beina initialized by said microprocessor and said pointers beina provided to said memory access arbitration unit by said first and second devices as part of said memory access requests.
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Accused Products
Abstract
A computer network for high-speed data communication, has a data transmission cable with a root and at least one leaf node. A signal conversion system (SCS) is attached to the root, and at least one client station is attached to a leaf node. The SCS consists of a transmitter that transmits down-stream data onto said cable in a first frequency band; and a receiver that receives data from said client stations on a second frequency band; wherein said down-stream data includes synchronization and acknowledgement signals. Each client station has a receiver that receives data on said first frequency band, and a transmitter that transmits data on a second frequency band according to synchronization signals received on said first frequency band.
The computer network is controlled by a method comprising transmitting down-stream from the signal conversion system (SCS) a control signal having synchronization information on a first frequency band, receiving said control signal at client stations, transmitting up-stream from said client stations to said SCS on a second frequency band, the transmission being timed with respect to said synchronization information, and acknowledging on said first frequency band successful receipt by said SCS of said up-stream transmission.
The client station'"'"'s transmission packets may include requests for reserved slots on said second frequency band for subsequent transmissions, and the SCS has a scheduler operable to determine a start time for requested reserved slots, and transmits the start time for the requested reserved slots. The client stations are operable to wait to continue transmission until after waiting for the start time.
Other systems and methods are disclosed.
128 Citations
2 Claims
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1. A parallel processing system for a high speed data communications modem, comprising:
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a. a first state machine controlled device that performs a first data communication function; b. a first register set addressable by said first device; c. a second state machine controlled device that performs a second data communication function; d. a second register set addressable by said second device; e. a microprocessor connected to said first and second register sets; f. a shared memory; g. a memory access arbitration unit connected to said first and second devices and to said shared memory, and operable to accept a memory access request from each of said first and second devices during each clock cycle of the parallel processing system and to access said shared memory in response to said memory access requests and; h. a register file connected to said microprocessor and to said first and second devices, said register file containing a pointer to an area of said shared memory for storing data associated with said first data communication function and a pointer to an area of said shared memory for storing data associated with said second data communication function, said first and second pointers beina initialized by said microprocessor and said pointers beina provided to said memory access arbitration unit by said first and second devices as part of said memory access requests.
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2. A memory access device connected to a plurality of communication processing devices and a memory, operable to provide memory access to each of said communication processing devices at an average rate of one memory access per clock cycle, comprising:
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a. a first pipeline stage for accepting a memory access request from each of said communication processing devices during a clock cycle, the first pipeline staae having; i. a priority encoder operable to select one of said plurality of communication processing devices for next access to said memory, ii. a plurality of address registers, each corresponding to one of said communication processing devices, each containing an address in said memory to be accessed by said corresponding processor! communication processing device, and iii. a plurality of acknowledgment lines each connecting said priority encoder with one of said address registers, iv. wherein said priority encoder causes an acknowledgment signal to be transmitted on said acknowledgment line connecting said priority encoder to said address register corresponding to said selected communication processing device; b. a second pipeline stage, connected to said first pipeline stage by a first plurality of pipeline registers, wherein the address contents of said address registers are clocked into said first plurality of pipeline registers, said second pipeline stage having; i. a plurality of read registers, each corresponding to one of said communication processing devices, ii. a multiplexer, connected to each said pipeline register, operable to select contents of said pipeline register containing the address corresponding to said selected communication processing device; and c. a third pipeline stage, connected to said second pipeline stage by an address pipeline register, connected to said multiplexer, and having; i. a memory having a contents at each of a plurality of addresses, connected to said address pipeline register, wherein the contents of said address register provides an address to be accessed in said memory; and ii. a memory bus connected to said memory; iii. wherein said memory is operable to write the contents at said address to be accessed onto said memory bus.
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Specification