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High-speed data communications modem

  • US 5,787,483 A
  • Filed: 09/22/1995
  • Issued: 07/28/1998
  • Est. Priority Date: 09/22/1995
  • Status: Expired due to Term
First Claim
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1. A parallel processing system for a high speed data communications modem, comprising:

  • a. a first state machine controlled device that performs a first data communication function;

    b. a first register set addressable by said first device;

    c. a second state machine controlled device that performs a second data communication function;

    d. a second register set addressable by said second device;

    e. a microprocessor connected to said first and second register sets;

    f. a shared memory;

    g. a memory access arbitration unit connected to said first and second devices and to said shared memory, and operable to accept a memory access request from each of said first and second devices during each clock cycle of the parallel processing system and to access said shared memory in response to said memory access requests and;

    h. a register file connected to said microprocessor and to said first and second devices, said register file containing a pointer to an area of said shared memory for storing data associated with said first data communication function and a pointer to an area of said shared memory for storing data associated with said second data communication function, said first and second pointers beina initialized by said microprocessor and said pointers beina provided to said memory access arbitration unit by said first and second devices as part of said memory access requests.

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