Methods for fabrication of thin film inductors, inductor networks, inductor/capactor filters, and integration with other passive and active devices, and the resultant devices

• US 5,788,854 A
• Filed: 09/26/1994
• Issued: 08/04/1998
• Est. Priority Date: 08/16/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: California Micro Devices Corporation (ON Semiconductor Corporation)
• Inventors: Desaigoudar, Chan M., Gupta, Suren
• Primary Examiner(s): Powell, William
• Application Number:
  US08/312,322
• Time in Patent Office: 1,408 Days
• Field of Search: 216/13, 216/16, 216/17, 216/18, 216/20, 216/22, 216/33, 216/38, 216/41, 216/56, 438/689, 438/710, 336/180, 336/200, 361/268, 361/270, 361/738, 361/748, 361/764, 361/766, 361/767
• US Class Current: 216/13
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: Y10T 29/49099 Coating resistive material on a base

Abstract

The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention. The inductor fabricated in accordance with this invention is connected to other passive or active components through metal interconnections in order to improve the frequency performance of the inductor. In certain embodiments, parasitic capacitance of the inductor is significantly reduced by fabricating inductor coils on dielectric bridges. In certain embodiments, a magnetic core of ferromagnetic material is used to improve the performance of the inductor at frequencies below about 100 MHz.

Claims

1. A method for fabricating an electronic device including at least two inductors and at least one capacitor, comprising the steps of:

forming on a first surface of substrate having two surfaces a first patterned conductive area comprising pads and a plate of at least one capacitor, said conductive areas being separated from each other;

forming a patterned dielectric layer above said plate, said dielectric layer having a via for each inductor in said device, said vias penetrating through said dielectric layer so that an electrical connection may be made by each said inductor to an associated one of said pads;

forming a second patterned conductive layer disposed on top of said dielectric layer and over at least part of said plate; and

forming a third patterned conductive layer comprising at least two inductors which provide desired inductance values, each of said inductors being electrically connected at one end thereof to said plate through one of said vias, and the other end of each of said inductors being electrically connected to an associated one of said pads.

2. A method as in claim 1 wherein said substrate is non-conductive.

3. A method as in claim 2 wherein said substrate comprises a ceramic material, glass, or quartz.

4. A method as in claim 2 wherein said first conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

5. A method as in claim 2 wherein said plate comprises two generally orthogonally aligned rectangular shapes.

6. A method as in claim 5 wherein said pads are generally linearly aligned with the long axis of at least one of said orthogonally aligned rectangular shapes.

7. A method as in claim 2 wherein said patterned dielectric layer comprises an oxide, nitride, or polyamide, or a combination thereof.

8. A method as in claim 2 wherein said second patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

9. A method as in claim 2 wherein said third patterned conductive layer comprises copper, aluminum, aluminum alloys, silver or gold.

10. A method as in claim 1 wherein said substrate comprises a conducting or semiconducting material, and which further comprises the step of forming a dielectric or insulating layer on said first surface of said substrate.

11. A method as in claim 10 wherein said conducting or semiconducting material comprises a metal, silicon, Al₂ O₃, or a conductive ferromagnetic material.

12. A method for fabricating an electronic device including at least two inductors and at least one capacitor, comprising the steps of:

selectively doping portions of a semiconductor substrate so as to increase the conductivity of said doped portions, said doped portions comprising a set of pads and a plate of at least one capacitor, said conductive areas being separated apart from each other;

forming a patterned dielectric layer above said plate, said dielectric layer having one via for each inductor in said device, said vias penetrating through said dielectric layer so that an electrical connection may be made to said plate;

forming a second patterned conductive layer disposed on top of said dielectric layer and over at least a portion of said plate; and

forming a third patterned conductive layer comprising at least two inductors which provide desired inductance values, each of said inductors being electrically connected at one end thereof to said plate through one of said vias, and the other end of each of said inductors being electrically connected to an associated one of said pads.

13. A method as in claim 12 wherein said first conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

14. A method as in claim 12 wherein said plate comprises two generally orthogonally aligned rectangular shapes.

15. A method as in claim 14 wherein said pads are generally linearly aligned with the long axis of at least one of said orthogonally aligned rectangular shapes.

16. A method as in claim 12 wherein said patterned dielectric layer comprises an oxide, nitride, or polyamide, or a combination thereof.

17. A method as in claim 12 wherein said second patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

18. A method as in claim 12 wherein said third patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

19. An electronic device including at least two inductors and at least one capacitor, comprising:

a first patterned conductive area comprising pads and a plate of at least one capacitor, said conductive areas being formed on a first surface of substrate having two surfaces and separated from each other;

a patterned dielectric layer formed above said plate, said dielectric layer having a via for each inductor in said device, said vias penetrating through said dielectric layer so that an electrical connection may be made by each said inductor to an associated one of said pads;

a second patterned conductive layer disposed on top of said dielectric layer and over at least part of said plate; and

a third patterned conductive layer comprising at least two inductors which provide desired inductance values, each of said inductors having an electrical connection at one end thereof to said plate through one of said vias, and an electrical connection to an associated one of said pads at the other end of each of said inductors.

20. A device as in claim 19 wherein said substrate is non-conductive.

21. A device as in claim 20 wherein said substrate comprises a ceramic material, glass, or quartz.

22. A device as in claim 20 wherein said first conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

23. A device as in claim 20 wherein said plate comprises two generally orthogonally aligned rectangular shapes.

24. A device as in claim 23 wherein said pads are generally linearly aligned with the long axis of at least one of said orthogonally aligned rectangular shapes.

25. A device as in claim 20 wherein said patterned dielectric layer comprises an oxide, nitride, or polyamide, or a combination thereof.

26. A device as in claim 20 wherein said second patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

27. A device as in claim 20 wherein said third patterned conductive layer comprises copper, aluminum, aluminum alloys, silver or gold.

28. A device as in claim 19 wherein said substrate comprises a conducting or semiconducting material, and which further comprises a dielectric or insulating layer on said first surface of said substrate.

29. A device as in claim 28 wherein said conducting or semiconducting material comprises a metal, silicon, Al₂ O₃, or a conductive ferromagnetic material.

30. An electronic device including at least two inductors and at least one capacitor, comprising:

selectively doped portions of a semiconductor substrate, said doped portions comprising a set of pads and a plate of at least one capacitor, said conductive areas being separated apart from each other;

a patterned dielectric layer above said plate, said dielectric layer having one via for each inductor in said device, said vias penetrating through said dielectric layer so that an electrical connection may be made to said plate;

a second patterned conductive layer disposed on top of said dielectric layer and over at least a portion of said plate; and

a third patterned conductive layer comprising at least two inductors which provide desired inductance values, each of said inductors having electrical connections at one end thereof to said plate through one of said vias, and an electrical connection to an associated one of said pads at the other end of each of said inductors.

31. A device as in claim 30 wherein said first conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

32. A device as in claim 30 wherein said plate comprises two generally orthogonally aligned rectangular shapes.

33. A device as in claim 32 wherein said pads are generally linearly aligned with the long axis of at least one of said orthogonally aligned rectangular shapes.

34. A device as in claim 32 wherein said patterned dielectric layer comprises an oxide, nitride, or polyamide, or a combination thereof.

35. A device as in claim 32 wherein said second patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.

36. A device as in claim 32 wherein said third patterned conductive layer comprises copper, aluminum, silver, gold, or an alloy thereof.