Method of making EEPROM cell device with polyspacer floating gate

• US 5,789,297 A
• Filed: 10/24/1996
• Issued: 08/04/1998
• Est. Priority Date: 09/23/1996
• Status: Expired due to Fees

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Wang, Chih-Hsien, Chen, Min-Liang, Chang, Thomas
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/736,390
• Time in Patent Office: 649 Days
• Field of Search: 438/266, 438/267, 438/304, 438/305, 438/593, 438/596
• US Class Current: 438/267
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

Claims

1. A method of fabricating an EEPROM cell on a semiconductor substrate, said method comprising:

forming a gate oxide on said substrate;

forming a first polysilicon layer on said gate oxide;

patterning a second photoresist on said first polysilicon layer;

etching said first polysilicon layer to form a select gate;

forming a first isolation layer on a side wall of said select gate;

forming a floating gate on said gate oxide adjacent to said first isolation layer;

forming a lightly doped drain by ion implantation;

forming a second isolation layer on a portion of said select gate, said floating gate, and a portion of said lightly doped drain;

forming a control gate on said second isolation layer; and

forming a heavily doped source and drain using ion implantation.

2. The method of claim 1, wherein forming said floating gate comprises forming a polysilicon spacer adjacent to said first isolation layer.

3. The method of claim 1, wherein said lightly doped drain region is e self aligned with said floating gate.