Method of adding on chip capacitors to an integrated circuit

• US 5,789,303 A
• Filed: 07/11/1996
• Issued: 08/04/1998
• Est. Priority Date: 11/28/1994
• Status: Expired due to Term

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Leung, Pak K., Emesh, Ismail T.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/680,286
• Time in Patent Office: 754 Days
• Field of Search: 438/238, 438/239, 438/240, 438/250, 438/381, 438/393, 148/DIG. 14
• US Class Current: 438/381
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: Y10S 148/014 Capacitor

Abstract

A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Claims

1. A method of providing a capacitor for an integrated circuit, the integrated circuit having interconnect metallization and an overlying passivation layer comprising a substantially planar surface;

the method comprising;

opening vias through the passivation layer for contacting the underlying interconnect metallization;

filling selected vias with conductive material and selectively depositing a layer of conductive material on the surface of the passivation layer and overlying at least one via of said selected vias to define a bottom electrode of a capacitor and to form an interconnection to the underlying interconnect metallization through the at least one via;

providing a capacitor dielectric on the bottom electrode, and providing on the capacitor dielectric a second conductive layer defining a top capacitor electrode, the top capacitor electrode extending laterally of the bottom electrode and overlying at least one other via of said selected vias to form an interconnection to the underlying interconnect metallization through the at least one other via, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

2. A method according to claim 1 wherein selectively depositing a layer of conductive material on the surface of the passivation layer comprises depositing overall a layer of conductive material and then patterning said layer to define a bottom electrode.

3. A method according to claim 1 wherein the step of depositing a first layer of conductive material on the surface of the passivation layer comprises filling one of said selected vias with conductive material.

4. A method according to claim 1 wherein providing the capacitor dielectric comprises depositing a layer of a ferroelectric dielectric.

5. A method according to claim 1 comprising depositing a layer of ferroelectric dielectric selected from lead zirconate titanate and doped lead zirconate titanate.

6. A method according to claim 1 wherein the underlying interconnect metallization comprises an aluminum alloy, and the steps of providing the capacitor structure comprise processing at a temperature below 500°

C.

7. A method according to claim 1 wherein the step of providing a second layer of conductive material comprises filling the at least one other via with conductive material.

8. A method according to claim 1 wherein providing the layer of conductive material forming the bottom electrode comprises forming a multilayer stack comprising a barrier layer and an adhesion layer.

9. A method according to claim 1 wherein providing the capacitor dielectric comprises selective deposition through a stencil mask.

10. A method according to claim 1 wherein providing the top electrode comprises selective deposition of the second conductive layer through a stencil mask.

11. A method according to claim 1 wherein depositing the capacitor dielectric and the top electrode comprises deposition overall and patterning by wet etching.

12. A method according to claim 1 comprising a further step of providing thereon a protecting layer.

13. A method according to claim 12 wherein the protecting layer is a layer of dielectric.

14. A method of adding an on-chip capacitor to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface, the method comprising forming capacitors on top of the passivation layer comprising:

defining vias through the passivation layer for contacting the interconnect metallization;

filling the vias with conductive material and forming a capacitor on the surface of the passivation layer by

providing a bottom electrode overlying at least one via of the vias filled with conductive material to form an interconnection from the bottom electrode to the underlying interconnect metallization,

providing on the bottom electrode a capacitor dielectric,

and providing a top electrode extending over the capacitor dielectric and over at least another via of the vias filled with conductive material to form an interconnection from the top electrode to the underlying interconnect metallization, thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor electrodes.

15. A method of adding capacitors to an integrated circuit chip comprising a substrate having active devices formed thereon, interconnect metallization and an overlying passivation layer having a planar surface with bond pad openings to the underlying metallization;

the method comprising;

forming capacitors on top of the passivation layer by steps comprising;

defining contact openings to the interconnect metallization by opening a plurality of vias through the passivation layer;

forming a capacitor on the surface of the passivation layer overlying the plurality of vias by providing a layer of conductive material to form a first electrode contacting the underlying interconnect metallization through one of the plurality of vias, providing a layer of a capacitor dielectric on the first electrode, and providing a second layer of conductive material defining a second electrode extending over the capacitor dielectric and extending laterally of the first electrode, contacting the underlying interconnect metallization through a second via of the plurality of vias thereby routing interconnections from each of the electrodes of the capacitor to the interconnect metallization of the underlying integrated circuit through the passivation layer underneath the conductive layers forming the capacitor.

16. A method according to claim 15 wherein a plurality of capacitors are provided on the passivation layer of the integrated circuit, and the method comprises coupling selected ones of the plurality of capacitors through the underlying interconnect metallization.

17. A method according to claim 15 wherein providing the capacitor dielectric comprises depositing a layer of a ferroelectric dielectric.

18. A method according to claim 17 comprising depositing a layer of ferroelectric dielectric selected, from lead zirconate titanate, doped lead zirconate titanate, barium strontium titanate and doped barium strontium titanate.

19. A method according to claim 15 wherein the underlying interconnect metallization comprises an aluminum alloy, and the steps of providing the capacitor structure comprise processing at a temperature below 500°

C.