Single poly memory cell and array

• US 5,789,776 A
• Filed: 09/18/1996
• Issued: 08/04/1998
• Est. Priority Date: 09/22/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG), NVX Corporation
• Original Assignee: NVX Corporation
• Inventors: Lancaster, Loren T., Hirose, Ryan T.
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/715,569
• Time in Patent Office: 685 Days
• Field of Search: 257/324, 257/408, 257/399, 257/296
• US Class Current: 257/296
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

Claims

1. A non-volatile semiconductor device comprising:

a semiconductor substrate;

a plurality of substantially parallel bit lines arranged in a first direction on said substrate;

a plurality of substantially parallel virtual ground lines arranged in a first direction on said substrate, each paired with one of said bit lines to form bit line/virtual ground line pairs;

a plurality of substantially parallel word lines arranged in a second direction on said substrate substantially orthogonally to said first direction, said word lines being insulated from said bit lines and virtual ground lines;

at least one memory cell section of an array of memory cells, each comprised of a single programmable memory transistor, and one memory cell residing at the each intersection of said word lines with said bit line/virtual ground line pairs;

programmable memory transistors having a source, a drain, a gate, and a charge storage layer that has programmable memory states that produce a depletion threshold voltage of magnitude less than a magnitude of a supply voltage when the memory transistor is erased and a enhancement threshold voltage when the memory transistor is programmed, each having a first connection on a drain end to one of said bit lines and having a second connection on a source end to said virtual ground line associated therewith;

biasing circuitry for applying selected read biasing voltages to said memory cells including a reference voltage applied to said virtual ground lines of magnitude no greater than the magnitude of said supply voltage and at least equal to the magnitude of said depletion threshold voltage, and a voltage greater than said reference voltage applied to said bit lines;

and sensing circuitry for sensing a current generated at said memory cell in accordance with the programmable state of said charge storage layer of said addressable memory transistor.

2. The device according to claim 1, wherein said bit line and said virtual ground line comprise a highly conductive metal and said word line comprise at least a polysilicon material.

3. The device according to claim 2, wherein said word line further comprise a metal silicide layer on top of said polysilicon material.

4. The device according to claim 1, wherein said bit line and said virtual ground line materially comprise a semiconductor region in said substrate of the same conductivity type as said source and said drain region and said word line materially comprise a highly conductive metal.

5. The device according to claim 1, wherein said memory transistors comprise SONOS tunneling metal insulator semiconductor field effect transistors.

6. The device according to claim 1, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type.

7. The device according to claim 1, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a first conductivity type;

and wherein said memory cell section further comprises a first well region of a second conductivity type formed in said substrate as to surround said memory stack units.

8. The device according to claim 1, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type;

and wherein said memory cell section further comprises a first well region of a first conductivity type formed in said substrate as to surround said memory cell section and wherein said device further comprises an additional second well region of the second conductivity type formed in said substrate as to surround at least said first well region.

9. The device according to claim 7, wherein means is provided to connect said substrate to said supply voltage and to connect said first well to a supply reference voltage, during a read operation.

10. The device according to claim 8, wherein means is provided to connect said substrate to said supply reference voltage and to connect said second well to said supply voltage and to additionally connect said first well to said supply reference voltage during a read operation.

11. The device according to claim 1, wherein said biasing circuitry for applying selected read biasing voltages provides means to:

pre-charge said bit line to a first pre-charge value equal to the supply potential;

pre-charge said virtual ground lines to a second pre-charge value equal to said reference voltage;

and selectively bias a pre-determined word line to a potential equal to said reference voltage applied to said virtual ground lines so that current will flow between said source and drain of memory transistors when the memory transistor is erased.

12. The device according to claim 11, wherein said biasing circuitry for applying selected read biasing voltage provides further means maintain said bit line potential at a value substantially equal to the supply voltage and to connect said virtual ground line to a load which serves to decrease said virtual ground line potential from said second pre-charge value toward the supply reference potential in the absence of current from the selected memory cell while said sensing circuitry amplifies the voltage difference between said reference potential and the potential that results on said virtual ground line.

13. The device according to claim 12, wherein said memory cell section further comprises a source segment isolation gate which provides means to selectively pre-charge virtual ground lines to said second pre-charge value in only one memory cell section.

14. A non-volatile semiconductor device comprising:

a semiconductor substrate;

a plurality of substantially parallel bit lines arranged in a first direction on said substrate;

a plurality of substantially parallel virtual ground lines arranged in a first direction on said substrate, each placed adjacent to at least one of bit lines to form an array of alternating bit lines and virtual ground lines which are individually electrically isolated;

a plurality of substantially parallel word lines arranged in a second direction on said substrate substantially orthogonally to said first direction, said word lines being insulated from said bit lines and virtual ground lines;

at least one memory cell section of an array of memory cells, each comprised of a single programmable memory transistor, and one memory cell residing at the each intersection of said word lines with said bit lines;

programmable memory transistors having a source, a drain, a gate, and a charge storage layer that has programmable memory states that produce a depletion threshold voltage of magnitude less than a magnitude of a supply voltage when the memory transistor is erased and a enhancement threshold voltage when the memory transistor is programmed, each said memory cell having a first connection on a drain end to said bit line associated therewith and a second connection on a source end to said virtual ground line, said second connection formed to a virtual ground line placed on a first side of even numbered bit line and to a virtual ground line on an other side of odd numbered bit lines;

biasing circuitry for applying selected read biasing voltages to said memory cells including a reference voltage applied to said virtual ground lines of magnitude no greater than the magnitude of said supply voltage and at least equal to the magnitude of said depletion threshold voltage, and a voltage greater than said reference voltage applied to said bit lines;

and sensing circuitry for sensing a current generated at said memory cell in accordance with the programmable state of said charge storage layer of said addressable memory transistor.

15. The device according to claim 14, wherein said bit line and said virtual ground line materially comprise a semiconductor region in said substrate of the same conductivity type as said source and said drain region and said word line materially comprise a highly conductive metal.

16. The device according to claim 14, wherein said memory transistors comprise SONOS tunneling metal insulator semiconductor field effect transistors.

17. The device according to claim 14, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type.

18. The device according to claim 14, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a first conductivity type;

and wherein said memory cell section further comprises a first well region of a second conductivity type formed in said substrate as to surround said memory stack units.

19. The device according to claim 14, wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type;

and wherein said memory cell section further comprises a first well region of a first conductivity type formed in said substrate as to surround said memory cell section and wherein said device further comprises an additional second well region of the second conductivity type formed in said substrate as to surround at least said first well region.

20. The device according to claim 18, wherein means is provided to connect said substrate to said supply voltage and to connect said first well to a supply reference voltage, during a read operation.

21. The device according to claim 19, wherein means is provided to connect said substrate to said supply reference voltage and to connect said second well to said supply voltage and to additionally connect said first well to said supply reference voltage during a read operation.

22. The device according to claim 14, wherein said biasing circuitry for applying selected read biasing voltages provides means to:

pre-charge said bit line to a first pre-charge value equal to the supply potential;

precharge said virtual ground lines to a second precharge value equal to said reference voltage;

and selectively bias a pre-determined word line to a potential equal to said reference voltage applied to said virtual ground lines so that current will flow between said source and drain of memory transistors when the memory transistor is erased.

23. The device according to claim 22, wherein said biasing circuitry for applying selected read biasing voltage provides further means maintain said bit line potential at a value substantially equal to the supply voltage and to connect said virtual ground line to a load which serves to decrease said virtual ground line potential from said second pre-charge value toward the supply reference potential in the absence of current from the selected memory cell while said sensing circuitry amplifies the voltage difference between said reference potential and the potential that results on said virtual ground line.

24. The device according to claim 22, wherein said memory cell section further comprises a source segment isolation gate which provides means to selectively pre-charge virtual ground lines to said second pre-charge value in only one memory cell section.

25. A semiconductor memory device comprised of:

semiconductor substrate;

an array of addressable MIS transistors arranged in rows and columns comprising a plurality of substantially parallel stripes oriented in a first direction in the surface of said substrate, said stripes comprising a dielectric region on said semiconductor substrate surface to provide means for lateral electrical isolation;

a plurality of channel regions in said substrate, each placed away from and between said stripes in a self-aligned manner;

a plurality of substantially parallel source and drain regions in the surface of said substrate which are perfectly self-aligned on a first edge to said strips and on another edge to said channel regions;

a conductive gate layer, patterned as at least one set of a plurality of rows to form MIS gates oriented in a second direction, substantially orthogonal to said first direction, each one of said channel regions including at least one of said gates;

an insulation layer over said channel regions between said gate and said channel regions;

biasing circuitry for applying selected read biasing voltages to said MIS transistors; and

sensing circuitry for sensing a current generated at said MIS transistors in accordance with the state of said addressable MIS transistors.

26. The device according to claim 25, wherein said addressable MIS transistors comprise SONOS tunneling metal insulator semiconductor field effect transistors.

27. The device according to claim 25, wherein said conductive gate layer comprise a metal silicide layer on top of a polysilicon material.

28. The device according to claim 25, wherein said substrate has a first conductivity type and said source and drain regions are semiconductor regions of a second conductivity type.

29. The device according to claim 25, wherein said substrate has a first conductivity type and said source and drain regions are semiconductor regions of a first conductivity type;

and wherein said array of addressable MIS transistors further comprises a first well region of a second conductivity type formed in said substrate as to surround said array of addressable MIS transistors.

30. The device according to claim 25, wherein said substrate has a first conductivity type and said source and regions are semiconductor regions of a second conductivity type;

and wherein said array of addressable MIS transistors further comprises a first well region of a first conductivity type formed in said substrate as to surround said array of addressable MIS transistors and wherein said device further comprises an additional second well region of the second conductivity type formed in said substrate as to surround at least said first well region.

31. The device according to claim 29, wherein means is provided to connect said substrate to said supply voltage and to connect said first well to a supply reference voltage, during a read operation.

32. The device according to claim 30, wherein means is provided to connect said substrate to said supply reference voltage and to connect said second well to said supply voltage and to additionally connect said first well to said supply reference voltage during a read operation.

33. The device according to claim 25, wherein said biasing circuitry for applying selected read biasing voltages provides means to:

pre-charge said drain regions to a first pre-charge value equal to the supply potential;

pre-charge said source regions to a second pre-charge value equal to a second voltage;

and selectively bias a pre-determined word line to a potential equal to said second voltage applied to said source regions so that current can flow between said source and drain of MIS transistors under favorable conditions.