Calibrating the DC-offset of amplifiers

• US 5,789,974 A
• Filed: 07/17/1996
• Issued: 08/04/1998
• Est. Priority Date: 07/17/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Mueck, Michael, Burra, Gangadhar, Ferguson, Paul F. Jr.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/682,102
• Time in Patent Office: 748 Days
• Field of Search: 330/2, 330/9, 330/51, 330/253, 330/257
• US Class Current: 330/2
• CPC Class Codes: H03F 1/304 and using digital means
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2203/45048 Calibrating and standardising a dif amp
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45968 by offset reduction

Abstract

The dc-offset voltage of an amplifier is calibrated by: (1) configuring the amplifier as a comparator, (2) using the output of the comparator to drive the up/down select input of an up/down counter, and (3) using the output count of the up/down counter to control: (a) a dc-offset correction voltage being: (i) applied across the inputs of the amplifier, or (ii) being used to adjust a voltage which controls an operating parameter of a device in the amplifier, or (b) switches which selectively adjust the effective size or operating conditions of a transistor or other device such that the dc-offset voltage of the amplifier is adjusted corresponding to the value of the output count. At the end of a calibration cycle, the output count of the up/down counter is maintained and is used to: (a) control a voltage which is applied permanently in series with one of the inputs of the amplifier or to an operating parameter control lead of a device in the amplifier, or (b) maintain the position of switches used to adjust the effective size or operating conditions of the transistor or other device in the amplifier to compensate for the offset voltage thereof.

Claims

1. An amplifier circuit, comprising:

an amplifier element having a first input and a second input, the amplifier element being arranged to be configured as an amplifier during a period of normal operation and to be configured as a comparator during a calibration period of the amplifier element;

a logic circuit coupled to an output of the amplifier element at least during the calibration period to receive an output signal from the output of the amplifier element and to output an offset compensation control signal representing an offset compensation voltage for the amplifier element; and

an offset compensation circuit including;

a positive voltage lead and a negative voltage lead, coupled, respectively, to the first input and the second input during the calibration period, and

an offset compensation control lead coupled to the logic circuit to receive the offset compensation control signal from the logic circuit, the offset compensation circuit being configured to provide, responsive to the offset compensation control signal, only the offset compensation voltage between the positive voltage lead and the negative voltage lead of the offset compensation circuit during all times when the amplifier element is receiving power.

2. The amplifier circuit as claimed in claim 1, wherein the logic circuit is configured to provide a digital output signal which is altered in response to the output signal from the amplifier element such that, responsive to a clock signal, the offset compensation voltage is increased if the output signal from the amplifier element is in a first logic state and decreased if the output signal from the amplifier element is in a second logic state.

3. The amplifier circuit as claimed in claim 2, wherein:

the logic circuit includes an up/down counter having an up/down select input and a count output, the output of the amplifier element being coupled to the up/down select input of the up/down counter at least during the calibration period; and

the offset compensation circuit includes a digital-to-analog converter having a digital input coupled to the count output of the up/down counter to receive an output count of the up/down counter as the offset compensation control signal.

4. An amplifier circuit, comprising:

an amplifier including;

an input to receive an input signal,

an output to provide an output signal, and

a plurality of primary devices coupled between the input and the output;

at least one secondary device, the at least one secondary device being substantially smaller than each of the plurality of primary devices; and

at least one switch coupled to at least one of the amplifier and the at least one secondary device to selectively couple the at least one secondary device to the amplifier to alter the effective size of at least one of the plurality of primary devices to compensate for an offset voltage of the amplifier.

5. The amplifier circuit as claimed in claim 4, wherein the at least one of the plurality of primary devices is a transistor in a current mirror of the amplifier.

6. The amplifier circuit as claimed in claim 4, wherein the amplifier is connected to be configured as a comparator during a calibration period, and wherein the amplifier circuit further comprises a logic circuit coupled to the output of the amplifier at least during the calibration period to receive a logic signal from the output of the amplifier, and the logic circuit is coupled to the at least one switch to provide the at least one switch with a control signal which, responsive to the logic signal from the output of the amplifier, selectively activates the at least one switch.

7. The amplifier circuit as claimed in claim 6, wherein the logic circuit is configured such that the control signal includes a digital count that, responsive to a clock signal, is increased if the logic signal from the output of the amplifier is in a first logic state and is decreased if the logic signal from the output of the amplifier is in a second logic state.

8. The amplifier circuit as claimed in claim 4, wherein the plurality of primary devices includes a differential pair of the primary transistors and the amplifier further includes a shorting switch arranged to couple together a pair of outputs of the differential pair during a portion of the calibration period.

9. An amplifier circuit, comprising:

an amplifier element arranged to be configured as an amplifier during a period of normal operation and to be configured as a comparator during a calibration period, the amplifier element including at least one device coupled to an internal node of the amplifier element, the at least one device having an operating parameter control lead to control an operating parameter of the at least one device;

a logic circuit coupled to an output of the amplifier element at least during the calibration period to receive an output signal from the output of the amplifier element and to output an offset compensation control signal; and

an offset compensation control circuit coupled to the logic circuit and to the operating parameter control lead of the at least one device to receive the offset compensation control signal from the logic circuit and provide a parameter control signal to the operating parameter control lead to control a particular operating parameter of the at least one device to compensate for an offset voltage of the amplifier element.

10. An amplifier circuit as claimed in claim 9, wherein the at least one device includes a transistor and the operating parameter control lead is coupled to a substrate biasing node of the transistor.

11. An amplifier circuit as claimed in claim 9, wherein the at least one device includes a transistor included in a differential pair of input transistors of the amplifier element.

13. An amplifier circuit as claimed in claim 9, wherein the logic circuit is configured such that the offset compensation control signal, responsive to a clock signal, is increased if the signal from the output of the amplifier element is in a first logic state and is decreased if the signal from the output of the amplifier element is in a second logic state.

23. The amplifier circuit as claimed in claim 9, wherein the offset compensation control circuit is configured such that the parameter control signal provided to the operating parameter control lead includes a parameter control voltage.

12. An amplifier circuit, comprising:

an amplifier connected to be configured as a comparator during a calibration period, the amplifier including;

an input to receive an input signal,

an output to provide an output signal, and

at least one transistor included in a current mirror of the amplifier, the at least one transistor being coupled to an internal node of the amplifier and having an operating parameter control lead to control an operating parameter of the at least one transistor;

a logic circuit coupled to the output of the amplifier at least during the calibration period to receive a signal from the output of the amplifier and to output an offset compensation control signal; and

an offset compensation control circuit coupled to the logic circuit and to the operating parameter control lead of the at least one transistor to receive the offset compensation control signal from the logic circuit and provide a parameter control signal to the operating parameter control lead to control a particular operating parameter of the at least one transistor to compensate for an offset voltage of the amplifier.

24. The amplifier circuit as claimed in claim 12, wherein the offset compensation control circuit is configured such that the parameter control signal provided to the operating parameter control lead includes a parameter control voltage.

14. An amplifier circuit, comprising:

an amplifier element arranged to be configured as an amplifier during a period of normal operation and to be configured as a comparator during a calibration period;

a logic circuit coupled to an output of the amplifier element at least during the calibration period to receive an output signal from the output of the amplifier element and to output an offset compensation control signal, the logic circuit being configured to, responsive to a clock signal, increase the offset compensation control signal if the signal from the output of the amplifier element is in a first logic state and decrease the offset compensation control signal if the signal from the output of the amplifier element is in a second logic state; and

an offset compensation control circuit coupled to the logic circuit and the amplifier element to receive the offset compensation control signal from the logic circuit and, responsive to the offset compensation control signal, to compensate for an offset voltage of the amplifier element.

15. An amplifier circuit, comprising:

means for detecting an offset voltage of an amplifier element during an offset calibration period in which the detecting means includes means for configuring the amplifier element as an amplifier during a period of normal operation and configuring the amplifier element as a comparator during a calibration period; and

means for compensating for the offset voltage of the amplifier element, the compensating means being coupled to the detecting means at least during the calibration period.

16. A method for controlling an offset voltage of an amplifier element, comprising the steps of:

configuring the amplifier element as a comparator during a calibration period;

coupling a controllable voltage source that generates only an offset compensation voltage for the amplifier element between a pair of inputs of the amplifier element;

responsive to an output of the amplifier element, generating an offset compensation control signal that controls the offset compensation voltage;

responsive to the offset compensation control signal, adjusting the offset compensation voltage until the offset compensation voltage approximates an inherent offset voltage of the amplifier element; and

configuring the amplifier element as an amplifier during a period of normal operation.

17. The method as claimed in claim 16, wherein the step of generating an offset compensation control signal responsive to the output of the amplifier element includes the steps of:

responsive to a first logic state at the output of the amplifier element, increasing a value of the offset compensation control signal; and

responsive to a second logic state at the output of the amplifier element, decreasing the value of the offset compensation control signal.

18. A method for compensating for an offset voltage of an amplifier including a primary device having a first size and at least one secondary device having a second size, the second size being substantially smaller than the first size, the method comprising the steps of:

detecting an offset voltage of the amplifier; and

responsive to a detected offset voltage, selectively coupling the at least one secondary device to an internal node of the amplifier such that the first size of the primary device is effectively increased or decreased by the second size of the secondary device so as to alter the offset voltage of the amplifier circuit.

19. The method as claimed in claim 18, wherein:

the step of detecting the offset voltage of the amplifier includes the step of configuring the amplifier as a comparator; and

the step of selectively coupling the at least one secondary device to the internal node of the amplifier responsive to the detected offset voltage includes the steps of;

responsive to a first logic state at an output of the amplifier, increasing an offset compensation control signal which controls the selective coupling of the at least one secondary device to the amplifier circuit, and

responsive to a second logic state at the output of the amplifier, decreasing the offset compensation control signal which controls the selective coupling of the at least one secondary device to the amplifier circuit.

20. A method for controlling an offset voltage of an amplifier element, comprising the steps of:

configuring the amplifier element as a comparator during a calibration period;

connecting a pair of inputs of the amplifier element to one of a common node and two nodes having known voltages thereon;

responsive to an output signal of the amplifier element, selectively adjusting a level of an operating parameter of at least one device included in or coupled to the amplifier element to compensate for the offset voltage of the amplifier element; and

configuring the amplifier element as an amplifier during a period of normal operation.

21. The method as claimed in claim 20, wherein the step of selectively adjusting the voltage of the operating parameter of the at least one device responsive to the output signal of the amplifier element includes the steps of:

responsive to a first logic state at the output of the amplifier element, increasing the level of the operating parameter of the at least one device; and

responsive to a second logic state at the output of the amplifier element, decreasing the level of the operating parameter of the at least one device.

25. The method of claim 20, wherein the step of selectively adjusting the level of the operating parameter of the at least one device includes selectively adjusting a voltage of the operating parameter of the at least one device.

22. A method for compensating for an offset voltage of an amplifier element including the septs of:

configuring the amplifier element as a comparator during a calibration period;

connecting a pair of inputs of the amplifier element to one of a common node and two nodes having known voltages thereon; and

responsive to a first logic state at an output of the amplifier element, increasing a value of the compensation signal that controls the offset compensation of the amplifier element;

responsive to a second logic state at the output of the amplifier element, decreasing the value of the compensation signal that controls the offset compensation of the amplifier element; and

configuring the amplifier element as an amplifier during a period of normal operation.