Digital-to-analog converter having enhanced current steering and associated method

• US 5,790,060 A
• Filed: 09/11/1996
• Issued: 08/04/1998
• Est. Priority Date: 09/11/1996
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Tesch, Bruce J.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): HUYNH, KIM NGOC
• Application Number:
  US08/714,019
• Time in Patent Office: 692 Days
• Field of Search: 341/118, 341/119, 341/144, 341/145, 341/153, 341/154
• US Class Current: 341/119
• CPC Class Codes: H03M 1/089 of temperature variations
• CPC Class Codes: H03M 1/687 Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
• CPC Class Codes: H03M 1/745 with weighted currents
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

A digital-to-analog converter includes a plurality of current cells, at least one cell in one embodiment including a pair of bipolar current switching transistors connected to a current source and a current summing bus in a current steering configuration so that one transistor is off while the other transistor is on. A temperature compensated control circuit is included for controlling the difference in base-emitter voltages of the bipolar current switching transistors based upon a temperature dependent bias voltage to compensate for a thermal voltage of the bipolar transistors. The temperature compensated control circuit preferably comprises a proportional to absolute temperature (PTAT) current source, and a steering pair of transistors connected to the PTAT current source and the pair of bipolar current switching transistors. The PTAT current source and steering transistors effectively bias the current switching transistors to account for the thermal voltage of the bipolar transistors. Method aspects of the invention are also disclosed.

Claims

1. A digital-to-analog converter comprising:

digital input means for receiving a plurality of digital input signals;

at least one output current summing bus; and

a plurality of current cells connected to said digital input means and said at least one output current summing bus, at least one of said current cells comprising

a current source,

a pair of bipolar current switching transistors connected to said current source and said at least one output current summing bus in a current steering configuration so that one transistor is off while the other transistor is on, said pair of bipolar current switching transistors having a proportion of current steering based upon a difference in base-emitter voltages and also based upon a thermal voltage, and

temperature compensated control means for controlling the difference in base-emitter voltages of said bipolar current switching transistors based upon a temperature dependent bias voltage to compensate for the thermal voltage.

2. A digital-to-analog converter according to claim 1 wherein said temperature compensated control means comprises means for controlling the difference in base-emitter voltages of said bipolar current switching transistors to provide a predetermined proportion of current steering over a relatively wide temperature range.

3. A digital-to-analog converter according to claim 1 wherein said temperature compensated control means comprises proportional to absolute temperature (PTAT) control means for controlling the difference in base-emitter voltages of said bipolar current switching transistors based upon absolute temperature.

4. A digital-to-analog converter according to claim 3 wherein said PTAT control means comprises:

a PTAT current source; and

a pair of steering transistors and associated bias resistors connected to said PTAT current source and said pair of bipolar current switching transistors.

5. A digital-to-analog converter according to claim 4 wherein said temperature compensated control means further comprises a buffer stage connected between said pair of steering transistors and said pair of current switching transistors.

6. A digital-to-analog converter according to claim 4 wherein each of said pair of steering transistors comprises a bipolar transistor.

7. A digital-to-analog converter according to claim 5 wherein said buffer stage comprises a pair of buffer transistors and associated constant current sources connected thereto.

8. A digital-to-analog converter according to claim 1 wherein the plurality of current cells are arranged in a split architecture with a first group of current cells for a first number of least significant bits and a second group of current cells for a second number of most significant bits.

9. A digital-to-analog converter according to claim 8 further comprising a resistor network connected between the first group of current cells and the at least one current summing bus.

10. A digital-to-analog converter according to claim 8 wherein said digital input means comprises:

a master register receiving the digital input signals;

a data buffer and level shifter connected to said master register; and

a slave register connected between said data buffer and level shifter and said plurality of current cells.

11. A digital-to-analog converter according to claim 10 wherein said digital input means further comprises a decoder connected between said data buffer and level shifter and said slave register for the second group of current cells for the second number of most significant bits.

12. A digital-to-analog converter according to claim 1 wherein the emitters of said pair of bipolar current switching transistors are connected together.

13. A digital-to-analog converter according to claim 12 wherein said current source is connected to said emitters of said pair of bipolar current switching transistors.

14. A digital-to-analog converter comprising:

digital input means for accepting a plurality of digital input signals;

at least one output current summing bus; and

a plurality of current cells connected to said digital input means and said at least one output current summing bus, at least one of said current cells comprising

a current source,

a pair of bipolar current switching transistors connected to said current source and said at least one output current summing bus in a current steering configuration so that one transistor is off while the other transistor is on, said pair of bipolar current switching transistors having a proportion of current steering based upon a difference in base-emitter voltages and also based upon a thermal voltage,

a proportional to absolute temperature (PTAT) source, and

a pair of steering transistors connected to said PTAT source and said pair of bipolar current switching transistors for controlling the difference in base-emitter voltages of said bipolar current switching transistors based upon the PTAT source to provide a predetermined proportion of current steering over a relatively wide temperature range to thereby compensate for the thermal voltage.

15. A digital-to-analog converter according to claim 14 further comprising a buffer stage connected between said pair of steering transistors and said pair of bipolar current switching transistors.

16. A digital-to-analog converter according to claim 15 wherein said buffer stage comprises a pair of buffer transistors and associated constant current sources connected thereto.

17. A digital-to-analog converter according to claim 14 wherein the plurality of current cells are arranged in a split architecture with a first group of current cells for a first number of least significant bits and a second group of current cells for a second number of most significant bits.

18. A digital-to-analog converter according to claim 17 further comprising a resistor network connected between the first group of current cells and the at least one current summing bus.

19. A digital-to-analog converter according to claim 17 wherein said digital input means comprises:

a master register receiving the digital input signals;

a data buffer and level shifter connected to said master register; and

a slave register connected between said data buffer and level shifter and said plurality of current cells.

20. A digital-to-analog converter according to claim 19 wherein said digital input means further comprises a decoder connected between said data buffer and level shifter and said slave register for the second group of current cells for the second number of most significant bits.

21. A digital-to-analog converter according to claim 14 wherein the emitters of said pair of bipolar current switching transistors are connected together.

22. A digital-to-analog converter according to claim 14 wherein said current source is connected to said emitters of said pair of bipolar current switching transistors.

23. A current cell comprising:

a current source;

a pair of bipolar current switching transistors connected in a current steering configuration so that one transistor is off while the other transistor is on, said pair of bipolar current switching transistors having a proportion of current steering based upon a difference in base-emitter voltages and also based upon a thermally dependent voltage; and

temperature compensated control means for controlling the difference in base-emitter voltages of said bipolar current switching transistors based upon a temperature dependent bias voltage to compensate for the thermally dependent voltage, said temperature compensated control means comprising

a proportional to absolute temperature (PTAT) current source, and

a pair of steering transistors and associated bias resistors connected to said PTAT current source and said pair of bipolar current switching transistors for controlling the difference in base-emitter voltages of said bipolar current switching transistors based upon absolute temperature.

24. A current cell according to claim 23 wherein said temperature compensated control means comprises means for controlling the difference in base-emitter voltages of said bipolar current switching transistors to provide a predetermined ratio of current steering over a relatively wide temperature range.

25. A current cell according to claim 23 wherein the emitters of said pair of bipolar current switching transistors are connected together.

26. A method of steering current in a current cell of a plurality of such current cells connected to an output current summing bus of a digital-to-analog converter, each current cell comprising a pair of current switching transistors connected together in a current steering configuration so that one transistor is off while the other transistor is on, the pair of current switching transistors having a proportion of current steering based upon a difference in transistor control voltages and also based upon a thermally dependent voltage, the method comprising the steps of:

receiving at least one digital input signal;

supplying a current to the pair of current switching transistors for steering based upon the digital input signal; and

controlling the difference in transistor control voltages of the current switching transistors based upon a temperature dependent bias voltage to compensate for the thermally dependent voltage.

27. A method according to claim 26 wherein the step of controlling comprises controlling the difference in transistor control voltages of said current switching transistors to provide a predetermined ratio of current steering over a relatively wide temperature range.

28. A method according to claim 26 wherein the step of controlling comprises controlling the difference in transistor control voltages based upon a source having a predetermined output as a function of temperature to compensate for the thermally dependent voltage.

29. A method according to claim 26 wherein the step of controlling comprises controlling the difference in transistor control voltages based upon a proportional-to-absolute temperature (PTAT) source.

30. A method according to claim 26 wherein the step of controlling further comprises controlling the difference in transistor control voltages temperature using a pair of steering transistors connected to the pair of current switching transistors.