Thin film transistor array and method of manufacturing thereof

• US 5,790,222 A
• Filed: 02/04/1997
• Issued: 08/04/1998
• Est. Priority Date: 06/14/1996
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Byeong-Koo
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): TON, MINH TOAN T
• Application Number:
  US08/795,376
• Time in Patent Office: 546 Days
• Field of Search: 349/39, 349/139, 349/147, 349/42, 257/59
• US Class Current: 349/139
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A TFT array having an improved aperture ratio with significantly increasing capacitive coupling between the pixel electrode and the drain bus line is disclosed. The TFT array includes a plurality of data bus line segments interconnected by the source electrode metallization. Further, a plurality of insulating layers are provided on the substrate to increase the separation between the pixel electrodes and the data bus lines.

Claims

1. A liquid crystal display device, comprising:

a substrate;

first and second data bus line segments provided on said substrate; and

a switching device provided on said substrate, said switching device having source and drain electrodes; and

an interconnect electricaly coupling said first and second data bus line segments, said interconnect including the same conductive material as said source and drain electrodes.

2. A liquid crystal display device in accordance with claim 1, wherein said switching device includes a thin-film transistor.

3. A liquid crystal display device in accordance with claim 2, wherein said source electrode and said interconnect constitute a single metal layer.

4. A liquid crystal display device in accordance with claim 1, further comprising:

a third data bus line segment provided on said substrate and spaced from said second data bus line segment; and

a storage capacitor, an electrode of said storage capacitor extending between said second and third data bus line segments.

5. A liquid crystal display device in accordance with claim 4, further comprising:

a connection portion electrically coupling said second and third bus line segments, said connection portion and said interconnect being formed of the same material.

6. A liquid crystal display device in accordance with claim 1, further comprising:

a gate bus line extending between said first and second data bus line segments.

7. A liquid crystal display device in accordance with claim 6, wherein said gate bus line extends in a first direction and said first and second bus line segments extend in a second direction substantially perpendicular to said first direction.

8. A liquid crystal display device in accordance with claim 1, further comprising:

a black matrix pattern provided over said switching device and said first and second data bus line segments, said black matrix pattern having an opening; and

a pixel electrode provided in said opening of said black matrix pattern, said pixel electrode being electrically coupled to another electrode of said switching device.

9. A liquid crystal display device in accordance with claim 1, further comprising:

a pixel electrode electrically coupled to said drain electrode of said switching device; and

a plurality of insulating layers provided disposed between said pixel electrode and said substrate.

10. A method of manufacturing a liquid crystal display comprising the steps of

depositing a first conductive layer on a substrate;

patterning said first conductive layer to form first and second spaced data bus line segments;

depositing an insulating layer on said substrate;

selectively removing portions of said insulating layer to form openings over portions of said first and second data bus line segments;

depositing a second conductive layer on said insulating layer and in said openings;

patterning said second conductive layer to provide an interconnect electrically coupling said first and second bus line segments; and

electrically coupling said interconnect to a doped region of a transistor formed on said substrate.

11. A method in accordance with claim 10, wherein said step of patterning said first conductive layer includes forming a third data bus line segment and a storage capacitor electrode, said third data bus line segment being spaced from said second data bus line segment, and said storage capacitor electrode extending between said first and second data bus line segments.

12. A method in accordance with claim 10, further comprising the step of:

depositing a black matrix pattern on said substrate, said black matrix pattern covering said first and second data bus lines and said transistor.

13. A method in accordance with claim 10, further comprising the steps of:

depositing a plurality of insulating layers on said substrate; and

depositing a pixel electrode on said plurality of insulating layers.