Bare die multiple dies for direct attach
First Claim
1. A chip package comprising:
- a first die having a first size and including wiring coupled to chip package primary input/output (I/O) interconnections; and
a second die coupled directly to the first die and having a second size smaller than the first size, the second die providing and receiving signals via the first die to and from the chip package primary I/O interconnections.
5 Assignments
0 Petitions
Accused Products
Abstract
A chip package includes a substrate formed from a first die and its attendant wiring interconnections, having a first thermal coefficient of expansion. The first die includes primary input/output (I/O) interconnections for the chip package. Also provided is a second die that includes escape wiring formed on that die and coupled to the primary I/O interconnections through the first die. The second die has a second thermal coefficient of expansion similar to the first thermal coefficient of expansion. The chip package also includes connectors that couple the primary I/O interconnections of the first die to a second level package. An interposer may be provided to couple the primary I/O interconnections to the second level package. The second die is smaller than the first die. The peripheral area of the first die is left exposed when the second die is coupled to the first die so that sufficient I/O interconnections may be formed for the primary I/O interconnections on the first die. The second die provides and receives signals which may include the second die'"'"'s primary I/O to and from the first die. Wiring may be shared between the first die and the second die in a manner optimal for design and manufacturing.
188 Citations
28 Claims
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1. A chip package comprising:
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a first die having a first size and including wiring coupled to chip package primary input/output (I/O) interconnections; and a second die coupled directly to the first die and having a second size smaller than the first size, the second die providing and receiving signals via the first die to and from the chip package primary I/O interconnections. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A chip package comprising:
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a substrate having interconnections; a first die having a first size and a first thermal coefficient of expansion, the first die including escape wiring coupled to the interconnections; coupling means for coupling the first die to the substrate; and a second die coupled directly to the first die having a second size smaller than the first size and a second thermal coefficient of expansion that is substantially the same as the first thermal coefficient of expansion, the second die providing and receiving external signals to and from the substrate via the escape wiring. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification