Low in-rush current power factor control circuit

• US 5,790,395 A
• Filed: 02/27/1997
• Issued: 08/04/1998
• Est. Priority Date: 02/27/1997
• Status: Expired due to Term

• Current Assignee: Thomas E. Hagen
• Original Assignee: Thomas E. Hagen
• Inventors: Hagen, Thomas E.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Vu, Bao Q.
• Application Number:
  US08/807,662
• Time in Patent Office: 523 Days
• Field of Search: 363/16, 363/44, 363/80, 363/89, 363/124, 323/207, 323/222, 323/908
• US Class Current: 363/89
• CPC Class Codes: H02M 1/0006 Arrangements for supplying an adequate voltage to the control circuit of converters
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low in-rush current power factor control circuit that provides near unity power factor, is capable of controlling and limiting the in-rush current that occurs when the circuit is initially supplied with an AC mains input voltage and is further capable of controlling the DC output voltage of the circuit from a level above to below the peak AC mains input voltage.

Claims

1. A low in-rush current power factor control circuit, the circuit having a ground, an AC mains input voltage with a peak voltage and a DC output voltage, the circuit for regulating power factor, for limiting in-rush current that occurs upon initially applying the AC mains input voltage to the circuit and for regulating DC output voltage from a level above to below the peak voltage of the AC mains input voltage, comprising:

(a) a first rectifier portion for rectifying the AC mains input to a full wave rectified output;

(b) a first energy storage device for storing energy drawn from the AC mains input, said first energy storage device disposed between said full wave rectified output and a first common point;

(c) a switch configured to be enabled and disabled by an enable/disable input, said switch when enabled adapted to draw energy through said first energy storage device whereby energy is stored within said first energy storage device, said switch when disabled adapted to release the energy stored in said first energy storage device, said switch disposed between said first common point and a second common point;

(d) a filter for filtering switching transients resulting from said switch switching from enabled to disabled and disabled to enabled, said filter disposed between said full wave rectified output and ground;

(e) a power factor control circuit configured for manipulating the enable/disable input of said switch to facilitate power factor regulation and DC output voltage regulation, said power factor control circuit having a current limiting input, a feedback input and an AC input tied to said full wave rectified output, said power factor control circuit tied to ground;

(f) a second rectifier portion for half-wave rectifying the released energy from said first energy storage device, said second rectifier portion disposed between said first common point and a third common point;

(g) a second energy storage device for storing the half-wave rectified released energy from said second rectifier portion, a DC output voltage maintained across said second energy storage device, said second energy storage device disposed between said third common point and said full wave rectified output;

(h) a current limiter tied to said power factor control circuits'"'"' current limiting input the current limiter configured for limiting in-rush current, said current limiter disposed between said second common point and ground; and

(i) a feedback portion for determining the level of said DC output voltage and sending said level to said power factor control circuits'"'"' feedback input.

2. The low in-rush current power factor control circuit of claim 1, wherein said feedback portion comprises a transistor.

3. The low in-rush current power factor control circuit of claim 1, wherein said feedback portion comprises a differential amplifier.

4. The low in-rush current power factor control circuit of claim 1, wherein said feedback portion comprises an opto-isolator.

5. The low in-rush current power factor control circuit of claim 1, wherein said first energy storage device is an inductor having a secondary winding with a voltage across said secondary winding and wherein said feedback portion utilizes said voltage across said secondary winding to determine the level of said DC output voltage.

6. The low in-rush current power factor control circuit of claim 1, wherein said power factor control circuits'"'"' AC input is a low level AC phase signal input, and wherein said low in-rush current power factor control circuit further comprises an AC phase timing network disposed between said full wave rectified output and ground, said AC phase timing network adapted to reduce said full wave rectified output to an acceptable low level for said power factor control circuits'"'"' low level AC phase signal input.

7. The low in-rush current power factor control circuit of claim 1, wherein said power factor control circuit has an inductor flux signal input and wherein said first energy storage device is an inductor having a secondary winding tied to said inductor flux signal input.

8. A low in-rush current power factor control circuit, the circuit having a ground, an AC mains input voltage with a peak voltage and a DC output voltage, the circuit for regulating power factor, for limiting in-rush current that occurs upon initially applying the AC mains input voltage to the circuit and for regulating DC output voltage from a level above to below the peak voltage of the AC mains input voltage, comprising:

(a) a first rectifier portion for rectifying the AC mains input to a full wave rectified output;

(b) a first energy storage device for storing energy drawn from the AC mains input, said first energy storage device disposed between said full wave rectified output and a first common point;

(c) a switch adapted to be enabled and disabled by an enable/disable input, said switch when enabled adapted to draw energy through said first energy storage device whereby energy is stored within said first energy storage device, said switch when disabled adapted to release the energy stored in said first energy storage device, said switch disposed between said first common point and a second common point;

(d) a filter for filtering switching transients resulting from said switch switching from enabled to disabled and disabled to enabled, said filter disposed between said full wave rectified output and ground;

(e) a power factor control circuit for manipulating the enable/disable input of said switch to facilitate power factor regulation and DC output voltage regulation, said power factor control circuit having a current limiting input, a feedback input and a low level AC phase signal input, said power factor control circuit tied to ground;

(f) an AC phase timing network disposed between said full wave rectified output and ground, said AC phase timing network adapted to reduce said full wave rectified output to an acceptable low level for said power factor control circuit'"'"' low level AC phase signal input;

(g) a second rectifier portion for half-wave rectifying the released energy from said first energy storage device, said second rectifier portion disposed between said first common point and a third common point;

(h) a second energy storage device for storing the half-wave rectified released energy from said second rectifier portion, a DC output voltage maintained across said second energy storage device, said second energy storage device disposed between said third common point and said full wave rectified output;

(i) a current limiter tied to said power factor control circuit'"'"' current limiting input for limiting in-rush current, said current limiter disposed between said second common point and ground; and

(j) a feedback portion for determining the level of said DC output voltage and sending said level to said power factor control circuit'"'"' feedback input.

9. The low in-rush current power factor control circuit of claim 8, wherein said feedback portion comprises a transistor.

10. The low in-rush current power factor control circuit of claim 8, wherein said feedback portion comprises a differential amplifier.

11. The low in-rush current power factor control circuit of claim 8, wherein said feedback portion comprises an opto-isolator.

12. The low in-rush current power factor control circuit of claim 8, wherein said first energy storage is means is an inductor having a secondary winding with a voltage across said secondary winding and wherein said feedback portion utilizes said voltage across said secondary winding to determine the level of said DC output voltage.

13. The low in-rush current power factor control circuit of claim 8, wherein said power factor control circuit has an inductor flux signal input and wherein said first energy storage device is an inductor having a secondary winding tied to said inductor flux signal input.

14. A low in-rush current power factor control circuit, the circuit having a ground, an AC mains input voltage with a peak voltage and a DC output voltage, the circuit for regulating power factor, for limiting in-rush current that occurs upon initially applying the AC mains input voltage to the circuit and for regulating DC output voltage from a level above to below the peak voltage of the AC mains input voltage, comprising:

(a) first rectifying means for rectifying the AC mains input to a full wave rectified output;

(b) an inductor for storing energy drawn from the AC mains input, said inductor having a secondary winding, said inductor disposed between said full wave rectified output and a first common point;

(c) switching means adapted to be enabled and disabled by an enable/disable input, said switching means when enabled adapted to draw energy through said inductor whereby energy is stored within said inductor, said switching means when disabled adapted to release the energy stored in said inductor, said switching means disposed between said first common point and a second common point;

(d) filtering means for filtering switching transients resulting from said switching means switching from enabled to disabled and disabled to enabled, said filtering means disposed between said full wave rectified output and ground;

(e) power factor control means for manipulating the enable/disable input of said switching means to facilitate power factor regulation and DC output voltage regulation, said power factor control means having a current limiting input, a feedback input, an AC input tied to said full wave rectified output and an inductor flux signal input tied to said secondary winding, said power factor control means tied to ground;

(f) second rectifying means for half-wave rectifying the released energy from said inductor, said second rectifying means disposed between said first common point and a third common point;

(g) energy storage means for storing the half-wave rectified released energy from said second rectifying means, a DC output voltage maintained across said energy storage means, said energy storage means disposed between said third common point and said full wave rectified output;

(h) current limiting means tied to said power factor control means'"'"' current limiting input for limiting in-rush current, said current limiting means disposed between said second common point and ground; and

(i) feedback means for determining the level of said DC output voltage and sending said level to said power factor control means'"'"' feedback input.

15. The low in-rush current power factor control circuit of claim 14, wherein said feedback means comprises a transistor.

16. The low in-rush current power factor control circuit of claim 14, wherein said feedback means comprises a differential amplifier.

17. The low in-rush current power factor control circuit of claim 14, wherein said feedback means comprises an opto-isolator.

18. The low in-rush current power factor control circuit of claim 14, wherein said first energy storage is means is an inductor having a secondary winding with a voltage across said secondary winding and wherein said feedback means utilizes said voltage across said secondary winding to determine the level of said DC output voltage.

19. A low in-rush current, power factor control circuit, the circuit having a ground, an AC mains input voltage with a peak voltage and a DC output voltage, the circuit for regulating power factor, for limiting in-rush current that occurs upon initially applying the AC mains input voltage to the circuit and for regulating DC output voltage from a level above to below the peak voltage of the AC mains input voltage, comprising:

a) a first rectifier portion for rectifying the AC mains input to a full waver rectified output;

b) a first energy storage device for storing energy drawn from the AC mains input, said first energy storage device disposed between said full waver rectified output and a first common point;

c) a switch configured to be enabled and disabled by an enable/disable input, said switch when enabled adapted to draw energy through said first energy storage device whereby energy is stored within said first energy storage device, said switch when disabled adapted to release the energy stored in said first energy storage device, said switch disposed between said first common point and a second common point;

d) a filter for filtering switching transients resulting from said switch switching from enabled to disabled and disabled to enabled, said filter disposed between said full wave rectified output and ground;

e) a power factor control circuit configured for manipulating the enable/disable input of said switch to facilitate power factor regulation and DC output voltage regulation, said power factor control circuit having a current limiting input, a feedback input and an AC input tied to said full wave rectified output, said power factor control circuit tied to ground;

f) a second rectifier portion for half-wave rectifying the released energy from said first energy storage device, said second rectifier portion disposed between said first common point and a third common point;

g) capacitor for storing the half-wave rectified released energy from said second rectifier portion, a DC output voltage maintained across said capacitor, said capacitor disposed between said third common point and said full wave rectified output;

h) a current limiter tied to said power factor control circuits'"'"' current limiting input the current limiter configured for limiting in-rush current, said current limiter disposed between said second common point and ground; and

i) a feedback portion for determining the level of said DC output voltage and sending said level to said power factor control circuits'"'"' feedback input.

20. A low in-rush current power factor control circuit, the circuit having a ground, an AC mains input voltage with a peak voltage and a DC output voltage, the circuit for regulating power factor, for limiting in-rush current that occurs upon initially applying the AC mains input voltage to the circuit and for regulating DC output voltage from a level above to below the peak voltage of the AC mains input voltage, comprising:

a) a first rectifier means for rectifying the AC mains input to a full wave rectified output;

b) an inductor for storing energy drawn from the AC mains input, said inductor having a secondary winding, said inductor disposed between said full wave rectified output and a first common point;

c) switching means adapted to be enabled and disabled by an enable/disable input, said switching means when enabled adapted to draw energy through said inductor whereby energy is stored within said inductor, said switching means when disable adapted to release the energy stored in said inductor, said switching means disposed between said first common point and a second common point;

d) filtering means for filtering switching transients resulting from said switching means switching from enabled to disabled and disabled to enabled, said filtering means disposed between said full wave rectified output and ground;

e) power factor control means for manipulating the enable/disable input of said switching means to facilitate power factor regulation and DC output voltage regulation, said power factor control means having a current limiting input, a feedback input, an AC input tied to said full wave rectified output and an inductor flux signal input tied to said secondary winding, said power factor control means tied to ground;

f) second rectifying means for half-wave rectifying the released energy from said inductor, said second rectifying means disposed between said first common point and a third common point;

g) capacitor for storing the half-wave rectified released energy from said second rectifying means, a DC output voltage maintained across said capacitor, said capacitor disposed between said third common point and said full wave rectified output;

h) current limiting means tied to said power factor control means current limiting input for limiting in-rush current, said current limiting means disposed between said second common point and ground; and

i) feedback portion for determining the level of said DC output voltage and sending said level to said power factor control circuits'"'"' feedback input.