Complementary network reduction for load modeling

• US 5,790,415 A
• Filed: 04/10/1996
• Issued: 08/04/1998
• Est. Priority Date: 04/10/1996
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Edwards, Tim J., Norton, Joseph W., Pullela, Satyamurthy, Dharchoudhury, Abhijit, Blaauw, David T.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/630,189
• Time in Patent Office: 846 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit "I-V" characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.

Claims

1. A method for providing a signal transition delay model for a circuit being designed, said method including the steps of:

translating passive transistors to an RC circuit model comprising only resistors and capacitors;

reducing said RC circuit model to a "pi" model circuit, the "pi" model circuit having a first capacitor and a second capacitor; and

determining an effective capacitance value from said "pi" model circuit, said effective capacitance being representative of an effective impedance for a portion of said circuit being designed;

wherein said effective capacitance is a function of the first capacitor and the second capacitor of the "pi" model circuit and transition delay.

2. The method as set forth in claim 1 and further including:

using said effective capacitance to determine a relationship between a capacitance value and a delay value for said portion of said circuit being designed;

setting said effective capacitance value to zero in said relationship;

determining a new delay value based upon such setting;

determining a new effective capacitance based upon said new delay value; and

updating said effective capacitance value to said new effective capacitance.

3. The method as set forth in claim 2 wherein said circuit being designed is to have a target delay value less than a predetermined delay value, said method further including:

determining if a convergence is present between a delay value calculated from said new effective capacitance and said target delay value; and

returning said process to said step of determining a new delay value if said convergence is absent.

4. The method as set forth in claim 1 and further including a method for correcting sensitivity characteristic values associated with circuit elements, said circuit elements and associated sensitivities comprising a file from which selected ones of said elements are designated to be included in a model circuit for use in specifying circuit elements and connections therebetween for a circuit being designed, said method for correcting sensitivity characteristic values comprising:

calculating approximate sensitivities for said circuit elements;

determining corrected sensitivities by applying a calculated correction factor;

selecting a most sensitive element having a highest corrected sensitivity;

calculating a predicted circuit delay change based upon using said model circuit including said most sensitive element;

increasing said most sensitive element size;

determining actual delay time of said model circuit;

determining whether said delay time of said model circuit meets a predetermined threshold; and

terminating said method if said delay time of said model circuit meets said predetermined threshold, said method being further operable otherwise for;

calculating a correction factor based upon said predicted delay change and said actual delay change, said calculated correction factor being available for determining corrected sensitivities for said circuit elements.

5. The method as set forth in claim 1 and further including:

applying a first circuit model to determine a circuit signal propagation delay;

periodically testing an accuracy characteristic of said circuit signal propagation delay; and

applying a more accurate second circuit model whenever said accuracy characteristic is determined to be outside of a predetermined threshold level.

6. A storage medium which is selectively coupled to a processing circuit, said processing circuit including a medium reading device selectively operable to read said storage medium and provide program signals representative of indicia present on said storage media to the processing circuit, said storage medium being selectively operable in combination with said processing circuit for providing a simulated delay model for a circuit being designed, said method comprising:

translating passive transistors to an RC circuit model comprising only resistors and capacitors;

reducing said RC circuit model to a "pi" model circuit, the "pi" model circuit having a first capacitor and a second capacitor; and

determining an effective capacitance value from said "pi" model circuit, said effective capacitance being representative of an effective impedance for a portion of said circuit being designed, wherein said effective capacitance is a function of the first capacitor and the second capacitor of the "pi" model circuit and transition delay.

7. The method as set forth in claim 6 and further including:

using said effective capacitance to determine a relationship between a capacitance value and a delay value for said portion of said circuit being designed;

setting said effective capacitance value to zero in said relationship;

determining a new delay value based upon such setting;

determining a new effective capacitance based upon said new delay value; and

updating said effective capacitance value to said new effective capacitance.

8. The method as set forth in claim 7 wherein said circuit being designed is to have a target delay value less than a predetermined delay value, said method further including:

determining if a convergence is present between a delay value calculated from said new effective capacitance and said target delay value; and

returning said process to said step of determining a new delay value if said convergence is absent.

9. A method for optimizing characteristics of a circuit being designed, said method comprising the steps of:

determining a required time at which a propagated input signal must arrive at predetermined nodes of a plurality of elements within the circuit, in order to enable the circuit to provide an output signal at a specified output time, said required time being measured from a predetermined input start time;

determining corresponding arrival times measured from said predetermined input start time, said corresponding arrival times being representative of times which said propagated input signal actually arrives at said predetermined nodes;

calculating a slack time at each of said predetermined nodes, said slack time being representative of a time difference between the arrival time and the required time;

selecting an element in accordance with a predetermined weighting function with regard to said slack times; and

changing a characteristic of said selected element;

wherein said step of determining corresponding arrival times further includes a delay model method for providing a simulated delay model for said circuit being designed, said delay model method comprising;

translating passive transistors to an RC circuit model comprising only resistors and capacitors;

reducing said RC circuit model to a "pi" model circuit, the "pi" model circuit having a first capacitor and a second capacitor; and

determining an effective capacitance value from said "pi" model circuit, said effective capacitance being representative of an effective impedance for a portion of said circuit being designed, wherein said effective capacitance is a function of the first capacitor and the second capacitor of the "pi" model circuit and transition delay.

10. The method as set forth in claim 9 and further including:

using said effective capacitance to determine a relationship between a capacitance value and a delay value for said portion of said circuit being designed;

setting said effective capacitance value to zero in said relationship;

determining a new delay value based upon such setting;

determining a new effective capacitance based upon said new delay value; and

updating said effective capacitance value to said new effective capacitance.

11. The method as set forth in claim 10 wherein said circuit being designed is to have a target delay value less than a predetermined delay value, said method further including:

determining if a convergence is present between a delay value calculated from said new effective capacitance and said target delay value; and

returning said process to said step of determining a new delay value if said convergence is absent.

12. A storage medium which is selectively coupled to a processing circuit, said processing circuit including a medium reading device selectively operable to read said storage medium and provide program signals representative of indicia present on said storage media to processing circuit, said storage medium being selectively operable in combination with said processing circuit for optimizing characteristics of a circuit being designed, by accomplishing the steps of:

determining a required time at which a propagated input signal must arrive at predetermined nodes of a plurality of elements within the circuit being designed, in order to enable the circuit being designed to provide an output signal at a specified output time, said required time being measured from a predetermined input start time;

determining corresponding arrival times measured from said predetermined input start time, said corresponding arrival times being representative of times which said propagated input signal actually arrives at said predetermined nodes;

calculating a slack time at each of said predetermined nodes, said slack time being representative of a time difference between the arrival time and the required time;

selecting an element in accordance with a predetermined weighting function with regard to said slack times; and

changing a size characteristic said selected element;

wherein said step of determining corresponding arrival times further includes a delay model method for providing a simulated delay model for said circuit being designed, said delay model method comprising;

translating passive transistors to an RC circuit model comprising only resistors and capacitors;

reducing said RC circuit model to a "pi" model circuit, the "pi" model circuit having a first capacitor and a second capacitor; and

determining an effective capacitance value from said "pi" model circuit, said effective capacitance being representative of an effective impedance for a portion of said circuit being designed, wherein said effective capacitance is a function of the first capacitor and the second capacitor of the "pi" model circuit and transition delay.

13. The method as set forth in claim 12 and further including:

using said effective capacitance to determine a relationship between a capacitance value and a delay value for said portion of said circuit being designed;

setting said effective capacitance value to zero in said relationship;

determining a new delay value based upon such setting;

determining a new effective capacitance based upon said new delay value; and

updating said effective capacitance value to said new effective capacitance.

14. The method as set forth in claim 13 wherein said circuit being designed is to have a target delay value less than a predetermined delay value, said method further including:

determining if a convergence is present between a delay value calculated from said new effective capacitance and said target delay value; and

returning said process to said step of determining a new delay value if said convergence is absent.