Circuit with built-in test and method thereof
First Claim
1. A built-in self test circuit method comprising the steps of:
- determining a response set of a circuit to be tested;
pruning the response set by removing all vertices of the response set that have a degree of one;
synthesizing a minimum required logic response of the response set by categorizing the pruned response set into a plurality of at least two categories, wherein no two adjacent vertices of the pruned response are in the same category, and carrying the categorization to the remainder of the response set; and
implementing a space compaction circuit according to the minimum required logic response, wherein the space compaction circuit is responsive to the circuit to be tested and outputs an error signal in response to a defect in the circuit to be tested.
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Accused Products
Abstract
A circuit with a built-in self test, comprising: a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.
94 Citations
10 Claims
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1. A built-in self test circuit method comprising the steps of:
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determining a response set of a circuit to be tested; pruning the response set by removing all vertices of the response set that have a degree of one; synthesizing a minimum required logic response of the response set by categorizing the pruned response set into a plurality of at least two categories, wherein no two adjacent vertices of the pruned response are in the same category, and carrying the categorization to the remainder of the response set; and implementing a space compaction circuit according to the minimum required logic response, wherein the space compaction circuit is responsive to the circuit to be tested and outputs an error signal in response to a defect in the circuit to be tested. - View Dependent Claims (2, 3, 4, 5)
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6. A circuit with a built-in self test, comprising:
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a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.
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7. A built-in self test circuit method comprising the steps of:
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dividing a set of outputs of a circuit to be tested into a plurality of subsets of outputs; determining a separate response set for each subset of outputs; for each response set;
pruning the response set by removing all vertices that have a degree of one, synthesizing a minimum required logic response of the response set by categorizing the pruned response set into a plurality of at least two categories, wherein no two adjacent vertices of the pruned response set are in the same category, carrying the categorization to a remainder of the response set and implementing a separate space compaction circuit according to each minimum required logic response,wherein the space compaction circuits are responsive to the circuit to be tested and at least one of the separate space compaction circuits outputs an error signal in response to a defect in the circuit to be tested. - View Dependent Claims (8)
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9. A circuit with a built in test, comprising:
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a circuit to be tested having outputs; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a plurality of space compaction circuits coupled to an output of the circuit to be tested, wherein each space compaction circuit is responsive to a subset of the outputs of the circuit to be tested to compact the subset of outputs of the circuit to be tested and produces a series of output signals when the input signals are applied to the circuit to be tested; and an analysis circuit coupled to the space compaction circuits and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals. - View Dependent Claims (10)
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Specification