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Digital phase-lock loop network

  • US 5,790,615 A
  • Filed: 12/11/1995
  • Issued: 08/04/1998
  • Est. Priority Date: 12/11/1995
  • Status: Expired due to Term
First Claim
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1. A phase-lock loop network for providing data sample-clock timing in a digital signal processing system receiving digital information defined by frames of multiple adjacent carriers transmitted simultaneously, wherein the digital processing system includes a data buffer receiving a number of data samples at predefined intervals and means for providing a synchronization signal corresponding to commencement of the predefined intervals, the network comprising:

  • means for providing a fixed frequency signal;

    means for providing a variable frequency signal;

    means for maintaining a count of the data samples within the data buffer; and

    means responsive to the synchronization signal for providing a data input clock according to said fixed frequency signal to the data buffer to thereby clock the number of data samples therein, and further responsive to the count of data samples within the data buffer for controlling the frequency of said variable frequency signal and providing a data output clock according to said variable frequency signal to the data buffer to thereby clock the number of data samples from the data buffer while maintaining a nominal number of data samples therein.

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