Digital phase-lock loop network

• US 5,790,615 A
• Filed: 12/11/1995
• Issued: 08/04/1998
• Est. Priority Date: 12/11/1995
• Status: Expired due to Term

• Current Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Original Assignee: Delco Electronics Corporation (General Motors Company)
• Inventors: Beale, Terrance Ralph, Boytim, Mathew Alan
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Roundtree, Joseph
• Application Number:
  US08/574,096
• Time in Patent Office: 967 Days
• Field of Search: 375/355, 375/356, 375/372, 375/376, 331/7, 331/11, 331/34, 331/40, 364/552, 364/571.01, 364/571.05, 370/208, 370/231, 370/236, 370/506, 370/512, 370/528, 370/530, 381/6, 381/24, 381/56
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04H 2201/20 digital audio broadcasting [DAB]
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06

Abstract

A digital phase-lock loop network that provides input and output clock signals to a digital data receiving system generally, and particularly to a data buffer contained therein, is disclosed. The digital phase-lock loop network provides bit-clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of the present invention is particularly suited for the Eureka-147 system which has become a worldwide standard for digital audio broadcasting (DAB) technology.

Claims

1. A phase-lock loop network for providing data sample-clock timing in a digital signal processing system receiving digital information defined by frames of multiple adjacent carriers transmitted simultaneously, wherein the digital processing system includes a data buffer receiving a number of data samples at predefined intervals and means for providing a synchronization signal corresponding to commencement of the predefined intervals, the network comprising:

means for providing a fixed frequency signal;

means for providing a variable frequency signal;

means for maintaining a count of the data samples within the data buffer; and

means responsive to the synchronization signal for providing a data input clock according to said fixed frequency signal to the data buffer to thereby clock the number of data samples therein, and further responsive to the count of data samples within the data buffer for controlling the frequency of said variable frequency signal and providing a data output clock according to said variable frequency signal to the data buffer to thereby clock the number of data samples from the data buffer while maintaining a nominal number of data samples therein.

2. The phase-lock loop network of claim 1 wherein said means for providing a fixed frequency signal includes:

a free running reference clock providing a reference clock signal having a first frequency; and

a first frequency divider responsive to said reference clock signal to provide said fixed frequency signal having a second frequency;

wherein said second frequency is a fraction of said first frequency.

3. The phase-lock loop network of claim 2 wherein said means responsive to a synchronization signal is further responsive to said fixed frequency signal to provide said data input clock as a predefined fraction thereof.

4. The phase-lock loop network of claim 2 wherein said means for providing a variable frequency signal is responsive to a frequency control signal provided by said means responsive to the synchronization signal to thereby vary the frequency of the variable frequency signal.

5. The phase-lock loop network of claim 4 wherein said means for providing a variable frequency signal includes a second frequency divider responsive to said reference clock signal and to said frequency control signal to provide said variable frequency signal as one of a third, fourth and fifth frequency signal;

wherein said third, fourth and fifth frequency signals are each predefined fractions of said first frequency.

6. The phase-lock loop network of claim 5 wherein said third frequency signal has a frequency of approximately 1/3 of said first frequency, said fourth frequency signal has a frequency of approximately 1/4 of said first frequency, and said fifth frequency signal has a frequency of approximately 1/5 of said first frequency.

7. The phase-lock loop network of claim 5 wherein said means responsive to the synchronization signal is further responsive to said variable frequency signal to provide said data output clock as a predefined fraction thereof.

8. The phase-lock loop network of claim 4 wherein said means for providing a variable frequency signal includes a voltage controlled oscillator responsive to said frequency control signal to provide said variable frequency signal as a varying fraction of said first frequency.

9. The phase-lock loop network of claim 1 wherein said means for maintaining a count of the data samples within the data buffer is a data buffer counter, said data buffer counter responsive to said data input clock signal to increment a count value of the data buffer counter with every clock pulse thereof, said data buffer counter comparing said count value to said nominal number of data samples and providing a count signal corresponding thereto.

10. The phase-lock loop network of claim 1 wherein said means responsive to the synchronization signal is a clock controller, said clock controller increasing the frequency of the variable frequency signal when the count of data samples within the data buffer is a predefined number above said nominal number of data samples, and decreasing the frequency of the variable frequency signal when the count of data samples within the data buffer is a predefined number below said nominal number of data samples.

11. The phase-lock loop network of claim 1 further including means responsive to the synchronization signal to initialize said means for maintaining a count of the data samples within the data buffer to an initial count.

12. In combination:

a digital signal processing system including a data buffer having a first input receiving a data input clock signal, a second input receiving a number of data samples in accordance with clock pulses of the data input clock signal, a third input receiving a data output clock signal, and an output providing the number of data samples in accordance with pulses of the data output clock signal; and

a phase-lock loop network for providing the data input and output clock signals, the network comprising;

a clock generator having a first input receiving a frequency control signal, a first output providing a first clock signal, and a second output providing a second clock signal, said second clock signal having a frequency defined by said frequency control signal;

a clock controller having a first input receiving said first clock signal and a first output providing the data input clock signal according thereto, a second input receiving said second clock signal and a second output providing the data output clock signal according thereto, a third input receiving a count signal corresponding to a count of the number of data samples within the data buffer, and a third output providing said frequency control signal in accordance with said count signal to thereby cause the frequency of said second clock signal to vary in accordance with the number of data samples within the data buffer, said second clock signal thereby maintaining a nominal number of data samples within the data buffer; and

a data buffer counter having a first input receiving the data input clock signal and an output providing said count signal, said data buffer counter incrementing the count of data samples with each clock pulse of the data input clock signal, comparing the count of data samples with said nominal number of data samples, and providing said count signal in accordance with deviation of the count of data samples from said nominal number of data samples.

13. The combination of claim 12 wherein the number of data samples corresponds to a frame of digital data defined by multiple adjacent carriers, wherein sequential frames of digital data are received at predefined intervals;

and wherein the digital signal processing system further includes means for providing a synchronization signal corresponding to commencement of the predefined intervals;

and wherein said clock controller includes a fourth input for receiving said synchronization signal, said clock controller providing said data input clock signal in response to said synchronization signal.

14. The combination of claim 13 wherein the phase-lock loop network further includes a data buffer counter initializer having an input receiving the synchronization signal and an output connected to a second input of said data buffer counter, said data buffer counter initializer operable to receive the synchronization signal and initialize the count of the data buffer counter to an initial count.

15. The combination of claim 12 wherein said clock generator includes:

a free running reference clock having an output providing a reference clock signal; and

a frequency divider having an input receiving said reference clock signal, providing said first clock signal as a fixed frequency division thereof at said first clock generator output, and providing said second clock signal as a variable frequency division thereof at said second clock generator output.

16. The combination of claim 15 wherein said frequency divider includes a plurality of frequency division portions receiving said reference clock signal and coupled to said second clock generator output, each of said frequency division portions defining a separate frequency division ratio, said frequency divider responsive to said frequency control signal to provide said second clock signal as a predetermined frequency division ratio of said reference clock signal.

17. The combination of claim 16 wherein said plurality of frequency division portions includes a first frequency division portion having a frequency division ratio of approximately 1/3, a second frequency division portion having a frequency division ratio of approximately 1/4, and a third frequency division portion having a frequency division ratio of approximately 1/5.

18. The combination of claim 12 wherein said clock generator includes:

a free running reference clock having an output providing a reference clock signal;

a frequency divider having an input receiving said reference clock signal and providing said first clock signal as a fixed frequency division thereof; and

a voltage-controlled oscillator having an input receiving said frequency control signal and an output providing said second clock signal in accordance therewith.