Input/output unit for a processor of a computer system having partitioned functional elements that are selectively disabled

• US 5,790,810 A
• Filed: 10/16/1996
• Issued: 08/04/1998
• Est. Priority Date: 10/16/1996
• Status: Expired due to Fees

• Current Assignee: Sarnoff Corporation (SRI International, Inc.)
• Original Assignee: David Sarnoff Research Center, Inc.
• Inventors: Kaba, James Timothy
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/731,491
• Time in Patent Office: 657 Days
• Field of Search: 395/750.01, 395/750.06, 395/750.08, 395/200.51, 395/653, 395/800.13, 395/182.03, 395/284, 395/800.15, 395/856
• US Class Current: 710/104
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

In a computer system containing at least one processor subsystems, an apparatus and a method for selective disabling processor subsystems using functional segmentation of the input/output circuitry. Each processor subsystem has a processor unit that is connected to an input/output unit. The input/output unit is partitioned into functional elements which are connected to other input/output units of other processor subsystems in the plurality of processor subsystems or to data sources and data sinks. The I/O unit further contains a functional element controller for selectively disabling and enabling the functional elements.

Claims

1. In a computer system containing at least one processor subsystem, apparatus, for selectively disabling certain elements of said processor subsystems, comprising:

a processor unit;

an input/output unit, connected to said processor unit, being partitioned into a plurality of functional elements; and

a functional element controller connected to each functional element, for selectively disabling said functional elements.

2. The apparatus of claim 1 wherein said functional element controller further comprises an instruction decoder, coupled to said processor unit and a processor subsystem controller, for decoding instructions that identify a particular functional element to disable.

3. The apparatus of claim 1 wherein the functional elements of said input/output unit comprises:

an input register, connected to said processor unit and connected to at least one other processor subsystem; and

an output register, connected to said processor unit and connected to at least one other processor subsystem.

4. The apparatus of claim 1 wherein the functional elements of said input/output unit further comprises:

an interprocessor communications interface, connected to said processor unit and connected to at least one other processor subsystem, for enabling each of said processor units in each of said processor subsystems to communicate to one another.

5. The apparatus of claim 4 wherein the functional elements of said input/output unit further comprises:

a storage device interface, connected to said interprocessor communications interface and to an information storage device, for coupling the processor with said information storage device.

6. The apparatus of claim 5 wherein said information storage device is an array of hard disk drives wherein each said disk drive in said array of hard disk drives is connected to each said storage device interface.

7. The apparatus of claim 5 wherein the said information storage device is an array of hard disk drives wherein each said hard disk drive is connected in a shared disk configuration to one or more said storage device interface.

8. A parallel processing computer comprising:

at least one controller; and

a plurality of processor subsystems each comprising;

a processor unit;

an input/output unit, connected to said processor unit, being partitioned into a plurality of functional elements; and

a functional element controller, connected to each functional element in said plurality of functional elements, for selectively disabling said functional elements.

9. The apparatus of claim 8 wherein said functional element controller further comprises an instruction decoder, coupled to said processor unit and a processor subsystem controller, for decoding instructions that identify a particular functional element to disable.

10. The apparatus of claim 8 wherein the functional elements of said input/output unit comprises:

an input register, connected to said processor unit and connected to at least one other processor subsystem; and

an output register, connected to said processor unit and connected to at least one other processor subsystem.

11. The apparatus of claim 10 wherein the functional elements of said input/output unit further comprises:

an interprocessor communications interface, connected to said processor unit and connected to at least one other processor subsystem, for enabling each of said processor units in each of said processor subsystems to communicate to one another.

12. The apparatus of claim 11 wherein the functional elements of said input/output unit further comprises:

a storage device interface, connected to said interprocessor communications interface and to an information storage device, for coupling the processor with said information storage device.

13. The apparatus of claim 12 wherein said information storage device is an array of hard disk drives wherein each said disk drive in said array of hard disk drives is connected to each said storage device interface.

14. The apparatus of claim 12 wherein the said information storage device is an array of hard disk drives wherein each said hard disk drive is connected in a shared disk configuration to one or more said storage device interface.

15. In a parallel processing computer containing a plurality of interconnected processor subsystems, where each processor subsystem contains a processor unit, an input/output unit partitioned into functional elements, a method for selectively disabling said functional elements, comprising the steps of:

selecting at least one of said processor subsystems containing functional elements to be bypassed;

choosing at least one of said functional elements;

disabling said chosen functional element; and

operating said functional elements that were not chosen.

16. The method of claim 15 wherein said functional element comprises an input register.

17. The method of claim 15 wherein said functional element comprises an output register.

18. The method of claim 15 wherein said functional element comprises an interprocessor communications interface.

19. The method of claim 15 wherein said choosing step further comprises the step of choosing a storage device interface as a disabled functional element.