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Extracting accurate and efficient timing models of latch-based designs

  • US 5,790,830 A
  • Filed: 12/29/1995
  • Issued: 08/04/1998
  • Est. Priority Date: 12/29/1995
  • Status: Expired due to Term
First Claim
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1. A model of a digital circuit, said model in a memory of a data processing system, the digital circuit having a first latch, a second latch and a third latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, and a clock signal driving said first clock pin, said second clock pin, and said third clock pin, said model comprising:

  • a model clock signal;

    a collapsed first model latch representing said first latch of said digital circuit and said second latch of said digital circuit;

    a first model clock pin of said first model latch driven by said model clock signal;

    a second model latch representing said third latch of said digital circuit;

    a second model clock pin of said second model latch driven by said model clock signal;

    means for verifying timing of said collapsed first model latch; and

    means for enabling time borrowing while verifying timing of said collapsed first model latch.

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