Extracting accurate and efficient timing models of latch-based designs

• US 5,790,830 A
• Filed: 12/29/1995
• Issued: 08/04/1998
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Segal, Russell B.
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/580,658
• Time in Patent Office: 949 Days
• Field of Search: 364/578, 364/488, 364/489, 364/490, 364/491, 395/500
• US Class Current: 706/6
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.

Claims

1. A model of a digital circuit, said model in a memory of a data processing system, the digital circuit having a first latch, a second latch and a third latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, and a clock signal driving said first clock pin, said second clock pin, and said third clock pin, said model comprising:

a model clock signal;

a collapsed first model latch representing said first latch of said digital circuit and said second latch of said digital circuit;

a first model clock pin of said first model latch driven by said model clock signal;

a second model latch representing said third latch of said digital circuit;

a second model clock pin of said second model latch driven by said model clock signal;

means for verifying timing of said collapsed first model latch; and

means for enabling time borrowing while verifying timing of said collapsed first model latch.

3. The model of claim 1 or claim 2 further comprising:

a timing arc between said first model latch and said collapsed second model latch.

4. The model of claim 3 further comprising:

a delay value on said timing arc.

5. The model of claim 3 further comprising:

a model data pin of said first model latch;

a clock to data timing arc between said first model clock pin and said model data pin of said first model latch; and

a model setup delay value on said clock to data timing arc.

6. The model of claim 5 wherein said model setup delay value is on the falling edge of said clock.

7. The model of claim 5 wherein said model setup delay value is on the rising edge of said clock.

8. The model of claim 4, said digital circuit having a setup delay on said second latch, said model further comprising:

a model data pin of said second model latch;

a clock to data timing arc between said second model clock pin and said model data pin of said second model latch; and

a model setup delay on said clock to data timing arc, wherein said model setup delay is equal to the sum of a cumulative delay from said first latch to said second latch and said setup delay minus said delay value.

9. The model of claim 1 or claim 2 further comprising:

a third model latch clocked by said model clock signal;

a delay to said third model latch wherein said delay is the minimum delay to any latch of said digital circuit clocked by said clock signal.

10. The model of claim 1 or claim 2 wherein said digital circuit also includes a first input, said first input driving said first latch, said model further comprising:

a model input representing said first input, said model input driving said first model latch.

2. A model of a digital circuit, said model in a memory of a data processing system, the digital circuit having a first latch, a second latch and a third latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, said first latch driving said second latch and said third latch, and a clock signal driving said first clock pin, said second clock pin, and said third clock pin, said model comprising:

a model clock signal;

a first model latch representing said first latch of said digital circuit;

a first model clock pin of said first model latch driven by said model clock signal;

a collapsed second model latch representing said second latch of said digital circuit and said third latch of said digital circuit;

a second model clock pin of said second model latch driven by said model clock signal;

means for verifying timing of said collapsed second model latch; and

means for enabling time borrowing while verifying timing of said collapsed second model latch.

11. A method, performed by a data processing system having a memory, comprising the steps of:

identifying a first latch in a digital circuit which is clocked by a clock;

building, in said memory, a first model latch representing the first latch and clocked by a model clock;

tracing a first branch of a transitive fanout from said first latch to a second latch clocked by said clock;

tracing a second branch of said transitive fanout from said first latch to a third latch clocked by said clock;

storing in said memory a maximum delay of a first delay from said first latch to said second latch and a second delay from said first latch to said third latch;

building a collapsed second model latch representing the second latch and the third latch in said memory clocked by said model clock;

building a timing arc between said first model latch and said second model latch;

annotating said timing arc with said maximum delay;

verifying timing of said collapsed second model latch; and

enabling time borrowing while verifying timing of said collapsed second model latch.

12. A method performed by a data processing system having a memory, comprising the steps of:

identifying a first set of latches in a digital circuit which are clocked by a first clock;

building a collapsed first model latch representing the first set of latches and clocked by a first model clock;

identifying a collapsed second set of latches clocked by a second clock from the combined transitive fanout of said first set;

determining a maximum delay between any latch of said first set and any latch of said second set;

building a collapsed second model latch representing the second set of latches and clocked by a second model clock;

building a first timing arc between said first model latch and said second model latch;

annotating said timing arc with said maximum delay;

verifying timing of said collapsed first and collapsed second model latches; and

enabling time borrowing while verifying timing of said collapsed first and collapsed second mode latches.

13. A method performed by a data processing system having a memory, comprising the steps of:

identifying a first set of latches in a digital circuit which are clocked by a clock;

building a collapsed first model latch representing said first set of latches and clocked by a model clock;

comparing a latch path length of a latch path ending at said collapsed first model latch to a maximum latch path length;

if said latch path length is greater than or equal to said maximum latch path length, then annotating said first model latch such that it is not capable of time borrowing;

verifying timing of the collapsed first model latch; and

enabling time borrowing when the collapsed first model latch is capable of time borrowing.

14. A model of a digital circuit having plural latches clocked by a clock, the model stored in a memory of a data processing system, comprising:

a model collapsed latch;

means for collapsing at least some of the plural latches clocked by the clock into the model collapsed latch, wherein a plurality of the latches clocked by the clock in the a digital circuit is represented by the model collapsed latch in the model;

means for verifying timing of said model collapsed latch;

means for enabling time borrowing while verifying timing of said model collapsed latch.

15. A model of a digital circuit in a memory of a data processing system comprising:

a first model latch representing a first latch of said digital circuit;

a second collapsed model latch representing a first plurality of latches of said digital circuit, wherein said first model latch drives said second collapsed model latch and is capable of time borrowing from said second collapsed model latch; and

means for enabling time borrowing while verifying timing of said second collapsed model latch.

16. A model of a digital circuit, said model in a memory of a date processing system, said model having a first latch, a second latch, a third latch, a fourth latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, a fourth clock pin of said fourth latch, said first latch driving said second latch, and said third latch, a first clock signal driving said first clock pin and said fourth clock pin, and a second clock signal driving said second clock pin and said third clock pin, said model comprising:

a first model clock signal;

a second model clock signal;

a first model latch representing said first latch of said digital circuit;

a first model clock pin of said first model latch driven by said first model clock signal;

a collapsed second model latch representing said second latch of said digital circuit and said third latch of said digital circuit;

a second model clock pin of said collapsed second model latch driven by said second model clock signal;

a third model latch representing said fourth latch of said digital circuit;

a third model clock pin of said third model latch driven by said first model clock signal;

means for verifying timing of the collapsed second model latch; and

means for enabling time borrowing while verifying timing of the collapsed second model latch.

17. A model of a digital circuit, said model in a memory of a data processing system, said model having a first latch, a second latch, a third latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, said first latch driving said third latch, said second latch driving said third latch, a first clock signal driving said first clock pin and said second clock pin, and a second clock signal driving said third clock pin, said model comprising:

a first model clock signal;

a second model clock signal;

a collapsed first model latch representing said first latch of said digital circuit and said second latch of said digital circuit wherein said collapsed first model latch is capable of time borrowing;

a first model clock pin of said collapsed first model latch driven by said first model clock signal;

a second model latch representing said third latch of said digital circuit;

a second model clock pin of said second model latch driven by said second model clock signal;

a timing arc between said collapsed first model latch and said second model latch;

means for verifying timing of the collapsed first model latch; and

means for enabling time borrowing while verifying timing of the collapsed first model latch.

18. The model of claim 17 wherein said second model latch is capable of time borrowing.

19. A method performed by a data processing system having a memory, comprising the steps of:

identifying a first latch in a digital circuit which is clocked by a first clock;

building a first model latch representing said first latch and clocked by a first model clock;

tracing a first branch of a transitive fanout from said first latch to a second latch clocked by a second clock;

tracing a second branch of said transitive fanout from said first latch to a third latch clocked by said second clock;

determining a maximum delay of a first delay from said first latch to said second latch and a second delay from said first latch to said third latch;

building a collapsed second model latch representing said second latch and said third latch and clocked by a second model clock;

building a timing arc between said first model latch and said collapsed second model latch;

annotating said timing arc with said maximum delay;

annotating said first model latch such that it is capable of time borrowing;

annotating said collapsed second model latch such that it is capable of time borrowing;

verifying the timing of the collapsed second model latch; and

enabling time borrowing while verifying timing of the collapsed second model latch.

20. The method of claim 19 further comprising the steps of:

verifying the timing of said model wherein said verification uses time borrowing.

21. A method performed by a data processing system having a memory, comprising the steps of:

identifying a first set of latches in a digital circuit which are clocked by a first clock;

building a collapsed first model latch representing said first set of latches and clocked by a first model clock;

identifying a second set of latches clocked by a second clock from the combined transitive fanout of said first set;

determining a maximum delay between any latch of said first set and any latch of said second set;

building a collapsed second model latch representing said second set of latches and clocked by a second model clock;

building a first timing arc between said collapsed first model latch and said collapsed second model latch;

annotating said timing arc with said maximum delay;

annotating said collapsed first model latch such that it is capable of time borrowing;

annotating said collapsed second model latch such that it is capable of tine borrowing;

verifying the timing of the collapsed first and collapsed second model latches; and

enabling time borrowing while verifying the timing of the collapsed first and collapsed second model latches.

22. A model in a memory of a data processing system of a digital circuit, the digital circuit having a first latch, a second latch and a third latch, a first clock pin of said first latch, a second clock pin of a said second latch, a third clock pin of said third latch, a clock signal driving said first clock pin, said second clock pin, and said third clock pin, a first input, said first input driving said first latch, a second input, said second input driving said second latch and said third latch, said model comprising:

a model clock signal;

a first model latch representing said first latch;

a first model clock pin of said first model latch driven by said model clock signal;

a collapsed second model latch representing said second latch and said third latch;

a second model clock pin of said collapsed second model latch driven by said model clock signal;

a first model input representing said first input of said digital circuit;

a second model input representing said second input of said digital circuit;

a first model arc connecting said first model input and said first model latch;

a second model arc connecting said second model input and said collapsed second model latch;

means for verifying the timing of the collapsed second model latch; and

means for enabling time borrowing while verifying the timing of the collapsed second model latch.