Method and apparatus for tracing any node of an emulation

• US 5,790,832 A
• Filed: 04/23/1996
• Issued: 08/04/1998
• Est. Priority Date: 04/23/1996
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG), Mentor Graphics Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Reblewski, Frederic, Barbier, Jean, Lepape, Olivier
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Irshadullah, M.
• Application Number:
  US08/639,248
• Time in Patent Office: 833 Days
• Field of Search: 364/578, 364/491, 364/490, 364/489, 395/51, 395/23, 395/141
• US Class Current: 703/28
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.

Claims

1. In an emulation system, a method for tracing hidden nodes of a circuit design, the method comprising the steps of:

(a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes;

(b) accessing values of the plurality of physically observable nodes; and

(c) determining the values of the hidden nodes based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the hidden nodes.

2. The method of claim 1, wherein the maintaining step (a) comprises the steps of:

generating a first list listing the physically observable nodes; and

generating a second list listing the hidden nodes, wherein each node of the second list is defined in terms of selected ones of the physically observable nodes.

3. The method of claim 2, wherein the maintaining step (a) further comprises the steps of:

generating a truth table vector for each node of the second list; and

storing the truth table vectors with the second list, wherein each truth table vector identifies the values of the corresponding hidden node as a function of the values of the physically observable nodes.

4. The method of claim 1, further comprising the step of:

outputting the values of the hidden nodes to a user.

5. A method for tracing any node of a circuit design in an emulator, the method comprising the steps of:

(a) generating a physically observable net list identifying a first plurality of nodes of the circuit design which can be physically observed in the emulator;

(b) creating a hidden net list identifying a second plurality of nodes of the circuit design, wherein each node of the second plurality of nodes is hidden in a logic element of the emulator;

(c) determining a first set of input nodes from the first plurality of nodes; and

(d) using the first set of input nodes to identify a value of a signal at a first hidden node, wherein the first hidden node is one of the second plurality of nodes.

6. The method of claim 5, further comprising the step of generating a first truth table vector which encodes a set of possible values for the first hidden node based on different values of the first set of input nodes.

7. The method of claim 6, further comprising the step of using the values of the first set of input nodes as an index into the truth table vector.

8. The method of claim 5, wherein the using step (d) comprises the steps of:

accessing the set of input nodes to identify a value of a signal at a second hidden node, wherein the second hidden node is one of the second plurality of nodes; and

using the value of the signal at the second hidden node to determine the value of the signal at the first hidden node.

9. A program storage device readable by an emulation system, the device embodying a program of instructions executable by the emulation system to perform method steps for tracing a node of a circuit design, wherein the node is hidden in a logic element of the emulation system, said method steps comprising:

(a) identifying a set of physically observable input signals corresponding to the node;

(b) indexing into a truth table vector using values of the set of physically observable input signals; and

(c) determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.

10. The program storage device of claim 9, further comprising the step of storing a set of node identifications corresponding to the set of physically observable input signals in an observable net file.

11. The program storage device of claim 9, further comprising the step of generating a hidden net list which stores the truth table vector.

12. The program storage device of claim 11, wherein the hidden net list also stores the node and a set identifier of the set of physically observable input signals.

13. A program storage device readable by a computer system, the device embodying a program of instructions executable by the computer system to perform method steps for tracing hidden nodes of a circuit design, said method steps comprising:

(a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes;

(b) accessing values of the plurality of physically observable nodes from an emulator coupled to the computer system upon receiving a request for the value of a first hidden node; and

(c) determining the value of the first hidden node based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the first hidden node.

14. The program storage device of claim 13, wherein the maintaining step (a) comprises the steps of:

generating a first list listing the physically observable nodes; and

generating a second list listing the hidden nodes, wherein each node of the second list is defined in terms of selected ones of the physically observable nodes.

15. The program storage device of claim 13, wherein the determining step (c) comprises the steps of:

accessing values of the plurality of physically observable nodes to identify a value of a second hidden node; and

using the value of the second hidden node to determine the value of the first hidden node.

16. The program storage device of claim 13, wherein the program of instructions are further to perform the method step of:

outputting the values of the hidden nodes to a user.

17. An emulation system which traces a node of a circuit design, the emulation system comprising:

a logic element in which the node is hidden;

means for identifying a set of physically observable input signals corresponding to the node;

means for indexing into a truth table vector using values of the set of physically observable input signals; and

means for determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.

18. The emulation system of claim 17, further comprising the means for storing a set of node identifications corresponding to the set of physically observable input signals.

19. The emulation system of claim 17, further comprising means for generating a hidden net list which stores the truth table vector.

20. The emulation system of claim 19, wherein the hidden net list also stores the node and a set identifier of the set of physically observable input signals.