Computer system including coprocessor devices simulating memory interfaces

• US 5,790,881 A
• Filed: 02/07/1995
• Issued: 08/04/1998
• Est. Priority Date: 02/07/1995
• Status: Expired due to Term

• Current Assignee: V-Silicon Semiconductors (HEFEI) Co., Ltd.
• Original Assignee: Sigma Designs Incorporated
• Inventors: Nguyen, Julien T.
• Primary Examiner(s): Harrity, John E.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/385,249
• Time in Patent Office: 1,274 Days
• Field of Search: 395/162, 395/163, 395/134, 395/135, 395/800.34, 395/500, 395/503, 395/527
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus. The coprocessor is disposed to receive data written from the master device, perform a coprocessing function on that data, and respond to a read data command from the master device with processing results. The coprocessor uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus. A general purpose computer system comprises a central processor and memory coupled to a PCI bus, a graphics processor and graphics memory coupled to the PCI bus, and a coprocessor coupled to the graphics processor and graphics memory. The coprocessor is adapted to compute, in response to data written to it by the graphics processor, a graphical function such as a 3D processing function, MPEG video compression or decompression, a raytracing function, or some related function in support of graphics processing. The coprocessor may communicate with the central processor and its memory using a memory access operation performed by the central processor, and may communicate with the graphics memory using a memory block transfer performed by the graphics processor. The coprocessor may emulate a memory wait condition or memory wait state using read-ready and write-ready flags which are readable by software executing on the general processor.

Claims

1. A computer system comprising:

a system bus;

a first processor coupled to said system bus;

a first memory bus coupled to said first processor;

a memory coupled to said first memory bus;

a graphics processor coupled to said system bus;

a graphics memory bus coupled to said graphics processor;

a graphics memory coupled to said graphics memory bus, said graphics memory being disposed to respond to a first set of addresses on said graphics memory bus; and

a coprocessor coupled to said graphics memory bus, said coprocessor being disposed to respond to a second set of addresses on said graphics memory bus so as to emulate a memory device;

wherein said coprocessor is disposed to receive a set of input data from said graphics memory bus when said graphics processor writes said input data to said graphics memory bus for one of said second set of memory addresses, said coprocessor is disposed to process said set of input data upon receipt to produce a set of output results, and said coprocessor is disposed to transmit said set of output results to said graphics memory bus when said graphics processor reads said output results from said graphics memory bus for one of said second set of memory addresses; and

a second coprocessor coupled to said graphics memory bus and disposed to respond to a third set of addresses on said graphics memory bus so as to emulate a memory device.

2. The system in claim 1, comprising a display;

wherein said coprocessor is disposed to compute, in response to said input data, a graphical function responsive to said input data; and

said graphics processor is disposed to present an image on said display responsive to said graphical function.

3. The system in claim 2, wherein said graphical function comprises a 3D graphics function, a graphics compression function, a graphics decompression function, a JPEG image function, an MPEG video function, or a raytracing function.

4. The system in claim 1, wherein said graphics processor is adapted to perform a memory operation communicating a data item between said graphics memory and said coprocessor.

5. A method for coupling computer system devices, said method comprising the steps of:

coupling a system bus to a processor;

directly coupling said processor and a memory to a memory bus, said memory bus comprising a set of control signal lines, a set of address lines, and a set of data lines;

directly coupling a coprocessor to said memory bus;

reserving a first set of memory addresses for said memory, and reserving a second set of memory addresses for said coprocessor;

disposing said coprocessor to emulate a memory device so as to receive a set of input data from said memory bus when said processor writes said input data to said memory bus for one of said second set of memory addresses;

disposing said coprocessor to emulate a memory device so as to process said set of input data upon receipt to produce a set of output results; and

disposing said coprocessor to emulate a memory device so as to transmit said set of output results to said memory bus when said processor reads said output results from said memory bus for one of said second set of memory addresses;

coupling a second coprocessor to said memory bus; and

reserving a third set of memory addresses for said second coprocessor.

6. The method in claim 5, further comprising a step of providing a read-ready flag at said coprocessor, said read-ready flag having a fist read-ready state representative of a condition wherein said coprocessor is ready to transmit said output results.

7. The method in claim 6, further comprising a step of disposing said processor to test said read-ready flag before performing a read operation on said memory bus for one of said second set of memory addresses.

8. The method in claim 5, further comprising a step of providing a write-ready flag at said coprocessor, said write-ready flag having a fist write-ready state representative of a condition wherein said coprocessor is ready to receive said input data.

9. The method in claim 8, further comprising a step of disposing said processor to test said write-ready flag before performing a write operation on said memory bus for one of said second set of memory addresses.

10. The method in claim 5, further comprising a step of disposing said coprocessor to receive a second set of data from said memory when said processor triggers a memory block transfer between a memory coupled to said memory bus and said coprocessor.

11. The method in claim 5, further comprising a step of disposing said coprocessor to transmit a second set of data to said memory when said processor triggers a memory block transfer between a memory coupled to said memory bus and said coprocessor.

12. The method in claim 5, wherein said processor is a graphics processor, said input data are graphics data, and said output results are graphics data, and comprising presenting an image on a display responsive to said output results.

13. A circuit comprising:

a memory bus having a set of control signal lines disposed to communicate a write enable control signal, a set of address lines, and a set of data lines;

a processor coupled directly to said memory bus, said processor having a memory address register coupled to said set of address lines and a memory data register coupled to said set of data lines;

a memory coupled to said memory bus, said memory being disposed to respond to a first set of memory addresses appearing on said set of address lines;

a coprocessor directly coupled to said memory bus, said coprocessor being disposed emulate a memory device so as to respond to a second set of memory addresses appearing on said set of address lines, and having means for performing a computation responsive to said set of data lines and a first state of said write enable control signal, and means for reporting a result of said computation responsive to said set of address lines and a second state of said write enable control signal; and

a second coprocessor coupled to said memory bus and disposed to respond to a third set of addresses appearing on said set of address lines on said memory bus.

14. The circuit in claim 13, further comprising a step of a read-ready flag at said coprocessor, said read-ready flag having a first read-ready state representative of a condition wherein said coprocessor is ready to transmit said result.

15. The circuit in claim 13, further comprising means for testing said read-ready flag before said processor performs a read operation on said memory bus for one of said second set of memory addresses.

16. The circuit in claim 13, further comprising a write-ready flag at said coprocessor, said write-ready flag having a first write-ready state representative of a condition wherein said coprocessor is ready to perform said computation.

17. A circuit as in claim 16, comprising means for testing said write-ready flag before said processor performs a write operation on said memory bus for one of said second set of memory addresses.

18. The circuit as in claim 13, wherein said control signal lines are disposed to communicate a block transfer control signal, and said memory is disposed to communicate a set of data items with said coprocessor responsive to said block transfer control signal.