Safety optimization in microprocessor-controlled implantable devices

• US 5,792,201 A
• Filed: 11/15/1996
• Issued: 08/11/1998
• Est. Priority Date: 07/13/1995
• Status: Expired due to Fees

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Inventors: Causey, James D. III, Yang, Min-Yaug
• Primary Examiner(s): Jastrzab, Jeffrey R.
• Application Number:
  US08/749,579
• Time in Patent Office: 634 Days
• Field of Search: 607/4, 607/5, 607/9, 607/11, 607/15, 607/27-29, 607/63
• US Class Current: 607/27
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/3718 Monitoring of or protection against external electromagnetic fields or currents
• CPC Class Codes: A61N 1/3931 Protecting, e.g. back-up systems

Abstract

A microprocessor-controlled implantable cardiac stimulating device having a normal mode, an intermediate mode, and a backup pacing mode is provided. The device switches from one mode to another in response to the detection of any one of an address error, parity error, opcode error, or watchdog timer error. The microprocessor is shut down during the delivery of a cardioversion or defibrillation shock in order to prevent signals produced by the microprocessor from being subjected to transient electrical signals. The interrupt registers of the microprocessor are also disabled during the delivery of a cardioversion or defibrillation shock. In an alternative embodiment, an implantable cardiac stimulating device is provided with redundant microprocessors in order to detect malfunctions of the microprocessors.

Claims

1. An implantable cardiac stimulating device comprising:

a first microprocessor;

a second microprocessor;

a primary pacing circuit;

a backup pacing circuit;

a comparator electrically coupled to each of the first and second microprocessors for receiving signals therefrom;

switching circuitry, coupled to each of the comparator, the primary pacing circuit, and the backup pacing circuit;

an interface coupled to each of the comparator and the first and second microprocessors; and

a data bus coupled to the interface, the data bus receiving signals from at least one signal source, and the interface receiving the signals from the data bus and communicating the signals to each of the first and second microprocessors, the first microprocessor processing the signals to produce a first processed signal, the second microprocessor processing the signals to produce a second processed signal, each of the first and second processed signals being communicated to the comparator, the comparator comparing the first and second processed signals in order to determine if the first and second microprocessors are functioning correctly;

wherein;

the switching circuitry activates the backup pacing circuit and deactivates the primary pacing circuit in response to a determination that the first and second microprocessors are not functioning correctly.

2. The device of claim 1, wherein the comparator determines that the first and second microprocessors are not functioning correctly if the first and second processed signals are not substantially identical.

3. The device of claim 1, wherein, if the first and second microprocessors are not functioning correctly, the comparator outputs an error signal, and wherein the first and second microprocessors are disabled in response to the error signal.

4. A method of operating an implantable cardiac stimulating device, the implantable stimulating device having a first microprocessor, a second microprocessor, a comparator electrically coupled to each of the first and second microprocessors for receiving signals therefrom, a data bus for transferring signals to and from at least one signal source and each of the first and second microprocessors, a primary pacing circuit, and a backup pacing circuit, the method comprising the steps of:

communicating a signal from the data bus to each of the first and second microprocessors, the first microprocessor processing the signal to produce a first processed signal, and the second microprocessor processing the signal to produce a second processed signal;

communicating each of the first and second processed signals to the comparator;

comparing the first and second processed signals using the comparator in order to determine if the first and second microprocessors are functioning correctly; and

deactivating the primary pacing circuit and activating the backup pacing circuit in response to a determination that the first and second microprocessors are not functioning correctly.

5. The method of claim 4, wherein the comparing step comprises the step of:

determining that the microprocessors are not functioning correctly when the first and second processed signals are not substantially identical.

6. The method of claim 4, further comprising the step of:

using a timer circuit to disable each of the first and second microprocessors when the comparator determines that the first and second microprocessors are not functioning correctly.