Signal conditioning circuit apparatus and method

• US 5,792,956 A
• Filed: 12/20/1995
• Issued: 08/11/1998
• Est. Priority Date: 08/11/1993
• Status: Expired due to Fees

• Current Assignee: BN Corporation LLC (Baker Hughes Company)
• Original Assignee: Bently Nevada Incorporated (General Electric Company)
• Inventors: Li, Don
• Primary Examiner(s): Williams, Hezron E.
• Assistant Examiner(s): MILLER, ROSE MARY
• Application Number:
  US08/575,935
• Time in Patent Office: 965 Days
• Field of Search: 73/661, 73/660, 73/579, 73/658, 73/649, 330/261, 330/296, 330/297, 330/257, 330/255, 330/253, 330/260, 330/267, 327/561, 327/562, 327/563, 327/336
• US Class Current: 73/660
• CPC Class Codes: G01H 1/003 of rotating machines G01H1/10 takes precedence
• CPC Class Codes: G01H 11/06 by electric means
• CPC Class Codes: H03F 3/347 in integrated circuits

Abstract

Apparatus and method utilized in conditioning an input signal from a transducer operatively coupled to a machine by self-biasing a circuit including an op-amp having an inverting signal input terminal, a non-inverting signal input terminal, bias voltage terminals and a signal output terminal. A power supply is operatively coupled to the bias voltage terminals via a single pair of supply lines and an input signal is directed to an input terminal of the op-amp. The op-amp outputs a conditioned signal to the supply lines which is superimposed with said DC bias voltage across the supply lines wherein the characteristics of the conditioned signal may be monitored via the supply lines.

Claims

1. A method for conditioning an input signal by self-biasing a circuit having an op-amp which includes an inverting signal input terminal, a noninverting signal input terminal, bias voltage terminals and a signal output terminal, the steps including:

providing a bias voltage for the op-amp through the bias voltage terminals,

directing an input signal into the inverting terminal of the op-amp,

outputting a conditioned signal from the output terminal, and

combining the conditioned signal with the bias voltage;

monitoring the conditioned signal across the bias voltage terminals;

whereby performance of the circuit is self-adjusted by characteristics of the conditioned signal such that the conditioned output signal rides on top of the bias voltage.

2. The method of claim 1 further including the step of monitoring the conditioned signal across the bias voltage terminals for monitoring the characteristics of the input signal.

3. The method of claim 1 wherein the step of providing the bias voltage for the op-amp through the bias voltage terminals includes the step of biasing the op-amp via a pair of supply/return lines operatively coupled between a power supply and the bias voltage terminals of the op-amp wherein the circuit includes a regulated self biasing means receiving current from the power supply and impressing a regulated DC bias voltage across the bias voltage terminals and the supply/return lines.

4. The method of claim 3 wherein the step of combining the conditioned signal with the bias voltage includes the step of buffering the conditioned signal onto the supply/return lines to be monitored by a means for monitoring characteristics of the conditioned circuit.

5. The method of claim 4 wherein the step of buffering the conditioned signal onto the supply/return lines includes the step of coupling a transistor to the output terminal of the op-amp and across the supply/return lines wherein the conditioned signal is buffered onto the supply/return lines to be monitored by the monitoring means.

6. The method of claim 5 further including the step of providing an active integrating amplifier (AIA) circuit having bias voltage terminals for DC biasing the AIA circuit.

7. The method of claim 6 further including the step of coupling the bias voltage terminals of the AIA circuit across the supply/return lines for receiving the regulated DC bias voltage for DC biasing the AIA circuit.

8. The method of claim 7 further including the step of applying an acceleration signal from a sensor monitoring vibration to an input of the AIA circuit wherein the acceleration signal has an amplitude proportional to vibration being monitored.

9. The method of claim 8 further including the step of integrating the acceleration signal applied to the input of the AIA circuit and outputting a resultant velocity signal from an output terminal of the AIA circuit.

10. The method of claim 9 wherein the step of directing the input signal into the inverting input terminal of the op-amp further includes the step of coupling the output terminal of the AIA circuit to the inverting input terminal of the op-amp wherein the velocity signal is directed to the inverting input terminal as the input signal to the op-amp.

11. The method of claim 10 wherein the step of conditioning the input signal further includes the step of amplifying the integrated input signal.

12. The method of claim 11 wherein the step of outputting the conditioned signal from the signal output terminal of the op-amp includes the step of outputting the conditioned signal as an integrated/amplified acceleration signal indicative of a magnitude of vibration being monitored by the sensor.

13. The method of claim 12 wherein the step of buffering the conditioned signal onto the supply lines includes the step of buffering the integrated/amplified acceleration signal onto the supply lines by coupling a transistor to the output terminal of the op-amp and across the supply/return lines wherein the integrated/amplified acceleration signal is buffered onto the supply/return lines to be monitored by the monitoring means.

14. A signal conditioning circuit comprising, in combination:

an op-amp having a first input terminal, a second input terminal, an output terminal and bias voltage terminals;

a regulated bias voltage means operatively coupled to a power supply via a pair of supply/return lines and to said bias voltage terminals for providing a bias voltage for said op-amp;

said first input terminal receiving and applying an input signal to said op-amp, and

said op-amp outputting a conditioned output signal to said output terminal;

a transistor operatively coupled to said output terminal of said op-amp and between the supply/return lines for receiving said conditioned signal and buffering said conditioned signal onto the supply/return lines which is superimposed with said regulated bias voltage across the supply/return lines wherein the supply/return lines double as means for supply current to said circuit and receiving and outputting said conditioned signal to a means for monitoring characteristics of said conditioned signal.

15. The circuit of claim 14 wherein said regulated biasing means includes a first zener diode operatively coupled to the supply/return lines.

16. The circuit of claim 15 wherein said regulated biasing means further includes:

a first branch including a first resistance means connected in series with said first zener diode;

said first branch operatively coupled across the supply/return lines, and the bias voltage means providing a current to said first zener diode through said first resistance means for biasing said first zener diode to function as a stable DC voltage regulator providing a regulated DC voltage.

17. The circuit of claim 16 wherein said regulated biasing means further includes:

said second input terminal of said op-amp operatively coupled to an intersection of said first resistance means and said first zener diode whereby said regulated DC voltage is applied to said second input terminal of said op-amp; and

means integrally formed within said op-amp for causing said DC regulated voltage to appear at said first input terminal of said op-amp.

18. The circuit of claim 17 wherein said regulated biasing means further includes:

a voltage divider network having a second branch including a plurality of serially connected resistance means;

said second branch operatively coupled across the supply/return lines, and

a fourth resistor having a first end connected to said first input terminal of said op-amp, and a second end connected to an intersection of two of said plurality of serially connected resistors of said second branch.

19. The circuit of claim 18 wherein said op-amp further includes:

means for substantially disallowing DC current flow through said fourth resistor, thereby allowing said regulated voltage at said first input terminal of said op-amp and said first end of said fourth resistor means to appear at said second end of said fourth resistor and across at least one of said plurality of serially connected resistance means.

20. The circuit of claim 19 wherein said regulated DC voltage across at least one of said plurality of serially connected resistance means draws a constant current through said second branch and said transistor providing means to compensate for any remaining current which is provided by the bias voltage means thereby providing said constant DC bias voltage across the supply/return lines and said bias voltage terminals of said op-amp.

21. The circuit of claim 20 further including an active integrating amplifier (AIA) circuit having a first input terminal operatively coupled to a sensor, a second input terminal, an output terminal operatively coupled to said first input terminal of said op-amp and bias voltage terminals coupled across the supply lines for receiving said DC bias voltage from said regulated biasing means for biasing said AIA circuit.

22. The circuit of claim 21 wherein said first input terminal of said AIA circuit receives an acceleration signal from the sensor monitoring machine vibration and integrates said acceleration signal into a velocity signal which is outputted at said output terminal of said AIA circuit and is provided to said first input terminal of said op-amp as said input signal.

23. The circuit of claim 22 wherein said input signal is a velocity signal which is amplified by said op-amp and outputted as an integrated/amplified acceleration signal at said output terminal of said op-amp where it is received by said transistor which is operatively coupled to said output terminal of said op-amp and between the supply lines.

24. The circuit of claim 23 wherein said transistor couples the integrated/amplified acceleration signal onto the supply lines to be superimposed with said DC bias voltage and to be monitored by a means for monitoring characteristics of said integrated/amplified acceleration signal.

25. A signal conditioning circuit comprising, in combination:

an op-amp having a first input terminal, a second input terminal, an output terminal and bias voltage terminals;

bias voltage means operatively coupled to said bias voltage terminals for providing a bias voltage for said op-amp;

said first input terminal receiving and applying an input signal to said op-amp, and

said op-amp outputting a conditioned output signal to said output terminal;

means for combining the conditioned signal with the bias voltage wherein the conditioned signal rides on top of the bias voltage;

wherein said bias voltage terminals are operatively coupled to the bias voltage means via a pair of supply/return lines;

further including a regulated biasing means operatively coupled to the supply/return lines and to the bias voltage terminals of said op-amp for receiving current from the bias voltage means and effecting a stable DC bias voltage across said bias voltage terminals of said op-amp and across the supply/return lines operatively coupled to said bias voltage terminals; and

further including a transistor operatively coupled to said output terminal of said op-amp and between the supply/return lines for receiving said conditioned signal and buffering said conditioned signal onto the supply/return lines which is superimposed with said regulated bias voltage across the supply/return lines wherein the supply/return lines double as means for supply current to said circuit and receiving and outputting said conditioned signal to a means for monitoring characteristics of said conditioned signal.

26. A method for conditioning an input signal by self-biasing a circuit having an op-amp which includes an inverting signal input terminal, a noninverting signal input terminal, bias voltage terminals and a signal output terminal;

the steps including;

providing a bias voltage for the op-amp through the bias voltage terminals,

directing an input signal into at least one signal input terminal of the op-amp,

outputting a conditioned signal from the output terminal, and

combining the conditioned signal with the bias voltage;

whereby performance of the amplifier is self-adjusted by characteristics of the conditioned signal such that the conditioned output signal rides on top of the bias voltage.