Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
First Claim
1. An integrated circuit, comprising:
- a gate conductor laterally defined between a pair of sidewall surfaces a dielectric spaced distance above a semiconductor substrate;
a first implant aligned with the sidewall surfaces, said first implant comprising a plurality of first dopant species arranged within the semiconductor substrate at a first concentration and a first concentration peak density; and
a second implant aligned with the sidewall surfaces, said second implant comprising a plurality of second dopant species arranged within the semiconductor substrate at a second concentration greater than the first concentration and a second concentration peak density shallower than the first concentration peak density.
3 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
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Citations
18 Claims
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1. An integrated circuit, comprising:
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a gate conductor laterally defined between a pair of sidewall surfaces a dielectric spaced distance above a semiconductor substrate; a first implant aligned with the sidewall surfaces, said first implant comprising a plurality of first dopant species arranged within the semiconductor substrate at a first concentration and a first concentration peak density; and a second implant aligned with the sidewall surfaces, said second implant comprising a plurality of second dopant species arranged within the semiconductor substrate at a second concentration greater than the first concentration and a second concentration peak density shallower than the first concentration peak density. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit, comprising:
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a semiconductor topography; a gate conductor extending across the semiconductor topography; a lightly doped drain (LDD) area defined within said semiconductor topography substantially adjacent said gate conductor, said LDD area having at least one region of heavy dopant concentration formed at a shallower depth than a region of light dopant concentration also defined within the LDD area; and a source/drain area defined within said semiconductor topography a spaced distance away from the gate conductor, said source/drain area having at least one region of heavy dopant concentration formed at a shallower depth than a region of light dopant concentration also defined within the source/drain area. - View Dependent Claims (17, 18)
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Specification