Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

• US 5,793,090 A
• Filed: 01/10/1997
• Issued: 08/11/1998
• Est. Priority Date: 01/10/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Fulford, H. Jim Jr., Hause, Fred N.
• Primary Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/781,445
• Time in Patent Office: 578 Days
• Field of Search: 257/344, 257/346, 257/408, 257/347, 438/302, 438/305
• US Class Current: 257/408
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.

Claims

1. An integrated circuit, comprising:

a gate conductor laterally defined between a pair of sidewall surfaces a dielectric spaced distance above a semiconductor substrate;

a first implant aligned with the sidewall surfaces, said first implant comprising a plurality of first dopant species arranged within the semiconductor substrate at a first concentration and a first concentration peak density; and

a second implant aligned with the sidewall surfaces, said second implant comprising a plurality of second dopant species arranged within the semiconductor substrate at a second concentration greater than the first concentration and a second concentration peak density shallower than the first concentration peak density.

2. The integrated circuit as recited in claim 1, wherein said gate conductor serves as an implant mask for said plurality of first and second dopant species.

3. The integrated circuit as recited in claim 1, wherein said plurality of first and second dopant species comprises n-type species.

4. The integrated circuit as recited in claim 1, wherein said plurality of first and second dopant species comprises p-type species.

5. The integrated circuit as recited in claim 1, wherein said plurality of first dopant species comprises atomic material of dissimilar chemical composition and atomic weight than the plurality of second dopant species.

6. The integrated circuit as recited in claim 1, wherein said plurality of first and second dopant species are forwarded into said semiconductor substrate at an acute angle relative to an upper surface of the semiconductor substrate.

7. The integrated circuit as recited in claim 6, wherein said acute angle comprises a range between approximately 45 degrees to approximately 83 degrees.

8. The integrated circuit as recited in claim 1, further comprises a third implant aligned with the sidewall surfaces, said third implant comprising a plurality of third dopant species arranged within the semiconductor substrate at a third concentration greater than the first concentration and a third concentration peak density shallower than the first concentration peak density.

9. The integrated circuit as recited in claim 8, wherein said third concentration is substantially identical to said second concentration and said third concentration peak density is at substantially the same depth as said second concentration peak density.

10. The integrated circuit as recited in claim 1, further comprising:

a spacer extending laterally from the pair of sidewall surfaces to form a pair of outer sidewall surfaces;

a third implant aligned with the outer sidewall surfaces, said third implant comprising a plurality of third dopant species arranged within the semiconductor substrate at a third concentration and a third concentration peak density; and

a fourth implant aligned with the outer sidewall surfaces, said fourth implant comprising a plurality of fourth dopant species arranged within the semiconductor substrate at a fourth concentration greater than the third concentration and a fourth concentration peak density shallower than the third concentration peak density.

11. The integrated circuit as recited in claim 10, wherein said first, second, third and fourth dopant species comprise n-type species.

12. The integrated circuit as recited in claim 10, wherein said first, second, third and fourth dopant species comprise p-type species.

13. The integrated circuit as recited in claim 10, wherein said plurality of third dopant species comprise atomic material of dissimilar chemical composition and atomic weight than the plurality of fourth dopant species.

14. The integrated circuit as recited in claim 10, wherein said plurality of third and fourth dopant species are forwarded into said semiconductor substrate at an acute angle relative to an upper surface of the semiconductor substrate.

15. The integrated circuit as recited in claim 14, wherein said acute angle comprises a range between approximately 45 degrees to approximately 83 degrees.

16. An integrated circuit, comprising:

a semiconductor topography;

a gate conductor extending across the semiconductor topography;

a lightly doped drain (LDD) area defined within said semiconductor topography substantially adjacent said gate conductor, said LDD area having at least one region of heavy dopant concentration formed at a shallower depth than a region of light dopant concentration also defined within the LDD area; and

a source/drain area defined within said semiconductor topography a spaced distance away from the gate conductor, said source/drain area having at least one region of heavy dopant concentration formed at a shallower depth than a region of light dopant concentration also defined within the source/drain area.

17. The integrated circuit as recited in claim 16, wherein said region of heavy dopant concentration within both the LDD area and the source/drain area comprises dopant species of similar type to dopant species within said region of light dopant concentration within respective said LDD area and said source/drain area.

18. The integrated circuit as recited in claim 16, wherein said region of heavy dopant concentration within the LDD area comprises dopant species of dissimilar atomic composition to dopant species within said region of light dopant concentration within the LDD area, and wherein said region of heavy dopant concentration within the source/drain area comprises dopant species of dissimilar atomic composition to dopant species within the region of light dopant concentration within the source/drain area.