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Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

  • US 5,793,090 A
  • Filed: 01/10/1997
  • Issued: 08/11/1998
  • Est. Priority Date: 01/10/1997
  • Status: Expired due to Term
First Claim
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1. An integrated circuit, comprising:

  • a gate conductor laterally defined between a pair of sidewall surfaces a dielectric spaced distance above a semiconductor substrate;

    a first implant aligned with the sidewall surfaces, said first implant comprising a plurality of first dopant species arranged within the semiconductor substrate at a first concentration and a first concentration peak density; and

    a second implant aligned with the sidewall surfaces, said second implant comprising a plurality of second dopant species arranged within the semiconductor substrate at a second concentration greater than the first concentration and a second concentration peak density shallower than the first concentration peak density.

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