Three dimensional processor using transferred thin film circuits

• US 5,793,115 A
• Filed: 09/29/1994
• Issued: 08/11/1998
• Est. Priority Date: 09/30/1993
• Status: Expired due to Term

• Current Assignee: Alanzor Research AB LLC (Intellectual Ventures LLC)
• Original Assignee: Kopin Corporation
• Inventors: Zavracky, Paul M., Zavracky, Matthew, Vu, Duy-Phach, Dingle, Brenda
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/315,027
• Time in Patent Office: 1,412 Days
• Field of Search: 257/777, 257/778, 257/790, 257/795, 257/798, 257/685, 257/686, 257/774, 437/974, 437/209, 437/220, 437/215, 437/211, 437/208
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/164 : Three dimensional processing

Abstract

A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

Claims

1. A data processing device comprising;

a first circuit layer formed in a semiconductor material and having a controller in the first circuit layer to control a data processing operation;

a second circuit layer formed in a thin film silicon material of a silicon-on-insulator (SOI) structure and having a logic unit in the second circuit layer that is connected with and controlled by the controller; and

an adhesive layer positioned between and securing the first circuit layer with the second circuit layer, the adhesive layer having interconnects extending between the first circuit layer and the second circuit layer to conduct control signals between the controller and the logic unit.

2. The data processing device of claim 1 wherein the first circuit layer further comprises a memory.

3. The data processing device of claim 1 wherein the second circuit layer further comprises a memory.

4. The data processing device of claim 1 further comprising a third circuit layer connected by interconnects with the second circuit layer, the interconnects extending through a second adhesive layer that secures the third circuit layer to the second circuit layer.

5. The data processing device of claim 1 wherein the adhesive layer comprises a polymeric material.

6. The data processing device of claim 1 wherein the adhesive layer comprises a thermally conductive epoxy.

7. The data processing device of claim 1 wherein the adhesive layer further comprises a particulate filler.

8. The data processing device of claim 7 wherein the particulate filler comprises metallic particles.

9. The data processing device of claim 1 wherein the logic unit circuit comprises an arithmetic logic unit.

10. An optoelectronic data processing device comprising;

a first circuit layer formed in a semiconductor material and having a controller in the first circuit layer to control a data processing operation;

a second circuit layer formed in a thin film silicon material of a silicon-on-insulator structure and having a light emitting device in the second circuit layer that is connected with and controlled by the controller; and

an adhesive layer positioned between and securing the first circuit layer with the second circuit layer, the adhesive layer having interconnects extending between the first circuit layer and the second circuit layer to conduct control signals between the controller and the logic light emitting device.

11. The data processing device of claim 10 wherein the first circuit layer further comprises a memory.

12. The data processing device of claim 10 wherein the second circuit layer further comprises a memory.

13. The data processing device of claim 10 further comprising a third circuit layer connected by interconnects with the first circuit layer, the interconnects extending through an adhesive layer that secures the third circuit layer to the first circuit layer.

14. The data processing device of claim 10 wherein the adhesive layer comprises a polymeric material.

15. The data processing device of claim 10 wherein the adhesive layer comprises a thermally conductive epoxy.

16. The data processing device of claim 10 wherein the adhesive layer further comprises a particulate filler.

17. The data processing device of claim 16 wherein the particulate filler comprises metallic particles.

18. The data processing device of claim 10 wherein the first circuit layer comprises an arithmetic logic unit.

19. A parallel processing device comprising;

a first circuit layer formed in a semiconductor material and having a controller and logic unit in the first circuit layer to control and perform a data processing operation;

a second circuit layer formed in a thin film silicon material of a silicon-on-insulator (SOI) structure and having a second controller and a second logic unit in the second circuit to control and perform a second data processing operation; and

an adhesive layer positioned between and securing the first circuit layer with the second circuit layer, the adhesive layer having interconnects extending between the first circuit layer and the second circuit layer to conduct control signals between the first circuit layer and the second circuit layer.

20. The processing device of claim 19 wherein the first circuit layer further comprises a memory.

21. The data processing device of claim 19 wherein the second circuit layer further comprises a memory.

22. The data processing device of claim 19 further comprising a third circuit layer connected by interconnects with the second circuit layer, the interconnects extending through a second adhesive layer that secures the third circuit layer to the second circuit layer.

23. The processing device of claim 19 wherein the adhesive layer comprises a polymeric material.

24. The processing device of claim 19 wherein the adhesive layer comprises a thermally conductive epoxy.

25. The processing device of claim 19 wherein the adhesive layer further comprises a particulate filler.

26. The processing device of claim 25 wherein the particulate filler comprises metallic particles.

27. The processing device of claim 19 wherein each logic unit circuit comprises an arithmetic logic unit.

28. A multi-layered data processing device comprising;

a first circuit layer formed in a semiconductor material and having a controller in the first circuit layer to control a data processing operation;

a second circuit layer formed in a thin film silicon material of a silicon-on-insulator structure and having a logic unit in the second circuit layer that is connected with and controlled by the controller;

a circuit routing layer positioned between the first circuit layer and the second circuit layer, the circuit routing layer having interconnects extending in a plane parallel to the first circuit layer which conduct signals between the first circuit layer and the second circuit; and

an adhesive layer positioned between and securing the first circuit layer with the second circuit layer, the adhesive layer having interconnects extending between the first circuit layer, the routing layer and the second circuit layer to conduct signals between the first circuit layer and the second circuit layer.

29. The data processing device of claim 28 wherein the first circuit layer further comprises a memory.

30. The data processing device of claim 28 wherein the second circuit layer further comprises a memory.

31. The data processing device of claim 28 further comprising a third circuit layer connected by interconnects with the second circuit layer, the interconnects extending through a second adhesive layer that secures the third circuit layer to the second circuit layer.

32. The data processing device of claim 28 wherein the adhesive layer comprises a polymeric material.

33. The data processing device of claim 28 wherein the adhesive layer comprises a thermally conductive epoxy.

34. The data processing device of claim 28 wherein the logic unit circuit comprises an arithmetic logic unit.